report_05-07-2025_04-31-29.html

Report generated on 07-May-2025 at 04:31:53 by pytest-html v3.2.0

Summary

920 tests ran in 23.25 seconds.

726 passed, 0 skipped, 194 failed, 0 errors, 0 expected failures, 0 unexpected passes

Results

Result Test TIDL Subgraphs Complete TIDL Offload Duration Links
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_727] 1 True 0.17
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_727'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_727', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=4007606 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a462a7170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_727/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_95] 1 True 0.28
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_95'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_95', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=4007613 parent=4006400 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f16a250 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14061s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.4810463611030926 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12336853 bytes MEM: Free's : 26 free's of 12336853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.4810463611030926 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_359] 1 True 0.64
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_359'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_359', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=4007599 parent=4006962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566385e71aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1522s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.1793964125987815 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 55130301 bytes MEM: Free's : 26 free's of 55130301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.1793964125987815 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_707] 1 True 0.15
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_707'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_707', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=4007593 parent=4006532 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a4d890 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_707/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_246] 1 True 0.29
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_246'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_246', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=4007598 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fc0d310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1632s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5952345220193207 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14845629 bytes MEM: Free's : 26 free's of 14845629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5952345220193207 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_66] 1 True 0.22
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_66'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_66', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4008720 parent=4006695 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187eb2a20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.131s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3323s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2319390021692218 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329653 bytes MEM: Free's : 26 free's of 12329653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2319390021692218 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_280] 1 True 0.30
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_280'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_280', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4008762 parent=4006396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b09b00a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1715s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6615599367246248 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21372093 bytes MEM: Free's : 26 free's of 21372093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6615599367246248 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_399] 1 True 0.42
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_399'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_399', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4008876 parent=4006168 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3059949730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1673s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7774847070124644 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76248589 bytes MEM: Free's : 26 free's of 76248589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7774847070124644 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_398] 1 True 0.60
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_398'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_398', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4008852 parent=4006497 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb30f9d570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.175s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2603s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8527259066878821 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76248589 bytes MEM: Free's : 26 free's of 76248589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8527259066878821 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_440] 1 True 0.36
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_440'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_440', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4008964 parent=4006008 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287e01765b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1828s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1831s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2365343556659742 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44613085 bytes MEM: Free's : 26 free's of 44613085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2365343556659742 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_354] 1 True 0.54
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_354'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_354', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4009070 parent=4006011 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c23850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.4547292952598463 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61036205 bytes MEM: Free's : 26 free's of 61036205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.4547292952598463 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_166] 1 True 0.20
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_166'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_166', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4009132 parent=4006129 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5917258e9950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5226s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5228s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7168700672786971 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12409021 bytes MEM: Free's : 26 free's of 12409021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7168700672786971 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_235] 1 True 0.27
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_235'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_235', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4009139 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cc3270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.21293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.21356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.21383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.21412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.21434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.21497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.21517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.21544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.21562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.21582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.21601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.9714347123447138 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14960829 bytes MEM: Free's : 26 free's of 14960829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.9714347123447138 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_741] 1 True 0.11
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_741'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_741', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4009291 parent=4006532 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a8ce60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_741/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_109] 1 True 0.18
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_109'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_109', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=4009864 parent=4006729 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e352a40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1497s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1199007728344401 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334293 bytes MEM: Free's : 26 free's of 12334293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1199007728344401 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_9] 1 True 0.12
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_9'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_9', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=4010064 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3875e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.4971346965420176 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332665 bytes MEM: Free's : 26 free's of 12332665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.4971346965420176 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_712] 1 True 0.10
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_712'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_712', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=4010107 parent=4006020 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea2c1d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_712/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_15] 1 True 0.17
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_15'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_15', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=4010544 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a462ea630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.11089s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.0269922563562315 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332921 bytes MEM: Free's : 26 free's of 12332921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.0269922563562315 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_706] 1 True 0.13
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_706'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_706', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=4010747 parent=4006129 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172592dcf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_706/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_245] 1 True 0.18
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_245'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_245', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=4010797 parent=4006695 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187baf9d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1697s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8709790989910001 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14845629 bytes MEM: Free's : 26 free's of 14845629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8709790989910001 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_273] 1 True 0.18
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_273'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_273', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=4011331 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46465b90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.0398386553249315 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21372093 bytes MEM: Free's : 26 free's of 21372093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.0398386553249315 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_162] 1 True 0.15
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_162'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_162', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=4011300 parent=4006168 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f305844a3f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.189s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8958862936537944 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12409021 bytes MEM: Free's : 26 free's of 12409021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8958862936537944 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_122] 1 True 0.23
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_122'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_122', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=4011424 parent=4006129 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172592dd30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5040s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5043s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.6658256703356533 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12371645 bytes MEM: Free's : 26 free's of 12371645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.6658256703356533 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_355] 1 True 0.31
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_355'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_355', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=4011777 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fdd8bd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2250s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.251226946476376 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 55130301 bytes MEM: Free's : 26 free's of 55130301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.251226946476376 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_191] 1 True 0.23
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_191'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_191', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=4011954 parent=4006497 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f5c9350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.27051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.27081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.27112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.27141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.27173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.27199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.27222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.27245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.27265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.27285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.27311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27853s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8887130294930148 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13444285 bytes MEM: Free's : 26 free's of 13444285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8887130294930148 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_515] 1 True 0.27
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_515'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_515', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=4012222 parent=4006400 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1aedc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1628s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5556859145238865 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68980029 bytes MEM: Free's : 26 free's of 68980029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5556859145238865 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_279] 1 True 0.33
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_279'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_279', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=4012547 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a349f9630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13454s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13457s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1996603513604385 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21765309 bytes MEM: Free's : 26 free's of 21765309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1996603513604385 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_736] 1 True 0.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_736'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_736', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=4012678 parent=4006020 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea709c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_736/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_96] 1 True 0.33
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_96'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_96', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=4012788 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb009c310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25091s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.609362052862478 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12336213 bytes MEM: Free's : 26 free's of 12336213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.609362052862478 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_725] 1 True 0.17
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_725'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_725', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=4012816 parent=4006063 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f700044b7e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_725/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_702] 1 True 0.13
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_702'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_702', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=4012819 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbb9ee10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_702/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_167] 1 True 0.25
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_167'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_167', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=4012948 parent=4006014 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e79f4ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.232s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5861s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5863s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8964720853440951 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12405949 bytes MEM: Free's : 26 free's of 12405949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8964720853440951 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_97] 1 True 0.24
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_97'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_97', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=4013039 parent=4006695 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187efbd30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.26614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.26663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.26687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.26716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.26745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.26770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.26793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.26815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.26836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.26858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.26880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.26901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.26928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.26951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.26973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.26998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.27018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.27037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.27063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.27084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.5213434864005158 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12335445 bytes MEM: Free's : 26 free's of 12335445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.5213434864005158 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_200] 1 True 0.17
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_200'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_200', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=4013634 parent=4006532 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5285440b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8773377156919435 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13468861 bytes MEM: Free's : 26 free's of 13468861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8773377156919435 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_275] 1 True 0.23
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_275'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_275', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=4013727 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f7029960 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.9844s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.10620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.029446861215754 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21372093 bytes MEM: Free's : 26 free's of 21372093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.029446861215754 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_438] 1 True 0.39
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_438'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_438', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=4014059 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fdd8d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1523s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1619992821015097 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 43318237 bytes MEM: Free's : 26 free's of 43318237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1619992821015097 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_198] 1 True 0.21
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_198'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_198', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=4013996 parent=4006129 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725848ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1620s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6444976815472121 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13419709 bytes MEM: Free's : 26 free's of 13419709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6444976815472121 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_433] 1 True 0.25
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_433'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_433', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=4014127 parent=4006330 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b4379220 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.235834491945529 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44613085 bytes MEM: Free's : 26 free's of 44613085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.235834491945529 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_234] 1 True 0.21
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_234'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_234', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=4014194 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34801a60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6033s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5871985443539739 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14807229 bytes MEM: Free's : 26 free's of 14807229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5871985443539739 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_317] 1 True 0.29
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_317'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_317', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=4014246 parent=4006396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b0881250 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2133923517729572 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29131517 bytes MEM: Free's : 26 free's of 29131517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2133923517729572 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_155] 1 True 0.19
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_155'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_155', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=4014672 parent=4006532 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a9e660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1647s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1649s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.624154709609332 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12412093 bytes MEM: Free's : 26 free's of 12412093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.624154709609332 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_158] 1 True 0.14
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_158'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_158', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=4015136 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3d5650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8844812879214515 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12405949 bytes MEM: Free's : 26 free's of 12405949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8844812879214515 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_710] 1 True 0.15
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_710'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_710', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=4015337 parent=4006729 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e39e890 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_710/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_157] 1 True 0.18
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_157'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_157', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=4015386 parent=4006599 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c21a60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1607s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1609s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7953039202279091 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12405949 bytes MEM: Free's : 26 free's of 12405949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7953039202279091 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_210] 1 True 0.22
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_210'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_210', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=4015429 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f69e3310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13053s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13056s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.722728239613601 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13444285 bytes MEM: Free's : 26 free's of 13444285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.722728239613601 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_735] 1 True 0.10
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_735'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_735', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=4016083 parent=4006695 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f07120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_735/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_126] 1 True 0.25
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_126'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_126', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=4016486 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6efb480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.21846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.21894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.21915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.21934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.21948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.21961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.21975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.21987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.21998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.22097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.22111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.22219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.22232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.22334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22406s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1787260529374006 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12369341 bytes MEM: Free's : 26 free's of 12369341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1787260529374006 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_729] 1 True 0.15
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_729'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_729', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=4016645 parent=4006063 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004930c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_729/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_723] 1 True 0.20
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_723'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_723', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=4016714 parent=4006695 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f090d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_723/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_703] 1 True 0.16
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_703'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_703', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=4016825 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46302e70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_703/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_724] 1 True 0.18
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_724'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_724', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=4017799 parent=4006497 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2faa5d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_724/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_728] 1 True 0.19
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_728'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_728', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=4017802 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46300cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_728/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_8] 1 True 0.24
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_8'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_8', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=4017816 parent=4006295 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4aa950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12658s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.5068778996879526 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12335673 bytes MEM: Free's : 26 free's of 12335673 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.5068778996879526 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_512] 1 True 0.38
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_512'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_512', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=4017803 parent=4006020 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e7a3b00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6529226061734039 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70421565 bytes MEM: Free's : 26 free's of 70421565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6529226061734039 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_357] 1 True 0.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_357'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_357', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=4017982 parent=4006396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b0889a30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.159s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1881s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2971931023029974 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58079421 bytes MEM: Free's : 26 free's of 58079421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2971931023029974 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_721] 1 True 0.14
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_721'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_721', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=4018484 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbe6ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_721/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_711] 1 True 0.16
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_711'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_711', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=4018746 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f030b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_711/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_316] 1 True 0.24
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_316'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_316', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=4018748 parent=4006168 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30581895c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1345s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.9538976202574978 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25746621 bytes MEM: Free's : 26 free's of 25746621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.9538976202574978 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_364] 1 True 0.32
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_364'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_364', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=4019477 parent=4006063 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70001e1920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7197239775404198 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 53360829 bytes MEM: Free's : 26 free's of 53360829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7197239775404198 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_164] 1 True 0.21
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_164'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_164', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=4019612 parent=4006396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b0894340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1688s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1693s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5086817617400469 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12409021 bytes MEM: Free's : 26 free's of 12409021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5086817617400469 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_274] 1 True 0.21
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_274'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_274', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=4019636 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d5da490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5562s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2528923055998955 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22551741 bytes MEM: Free's : 26 free's of 22551741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2528923055998955 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_100] 1 True 0.26
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_100'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_100', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=4019689 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46301540 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1372s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.468293999695359 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12336853 bytes MEM: Free's : 26 free's of 12336853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.468293999695359 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_717] 1 True 0.12
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_717'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_717', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=4019777 parent=4006168 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058459f90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_717/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_479] 1 True 0.51
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_479'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_479', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=4019844 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fdd8b90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1518s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1520s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.9394178685216726 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34485661 bytes MEM: Free's : 26 free's of 34485661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.9394178685216726 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_514] 1 True 0.42
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_514'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_514', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=4020233 parent=4006400 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1c0980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3033s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3036s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5753160769902758 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68980029 bytes MEM: Free's : 26 free's of 68980029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5753160769902758 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_394] 1 True 0.65
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_394'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_394', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=4020351 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbe8180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2034s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2036s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.5493659424356028 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74309261 bytes MEM: Free's : 26 free's of 74309261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.5493659424356028 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_475] 1 True 0.35
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_475'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_475', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=4020521 parent=4006014 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7684fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5809724461383695 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33432861 bytes MEM: Free's : 26 free's of 33432861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5809724461383695 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_392] 1 True 0.63
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_392'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_392', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=4020520 parent=4006129 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172593c610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1587s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8884231400538706 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74309261 bytes MEM: Free's : 26 free's of 74309261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8884231400538706 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_94] 1 True 0.25
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_94'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_94', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=4020545 parent=4006168 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058457a70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3541s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3542s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.6899879817966053 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12336213 bytes MEM: Free's : 26 free's of 12336213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.6899879817966053 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_151] 1 True 0.13
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_151'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_151', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=4020783 parent=4006396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b0895620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8919291023421917 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12405949 bytes MEM: Free's : 26 free's of 12405949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8919291023421917 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_436] 1 True 0.34
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_436'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_436', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=4021377 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4602ef90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3504s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.109170072935088 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42023261 bytes MEM: Free's : 26 free's of 42023261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.109170072935088 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_121] 1 True 0.21
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_121'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_121', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=4021382 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3e3b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2146967594132017 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12371645 bytes MEM: Free's : 26 free's of 12371645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2146967594132017 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_152] 1 True 0.32
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_152'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_152', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=4021582 parent=4006497 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2faae7a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10672s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.8888673050290692 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12409021 bytes MEM: Free's : 26 free's of 12409021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.8888673050290692 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_154] 1 True 0.17
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_154'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_154', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=4021446 parent=4006729 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3a90f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1529s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.9837331681763704 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12405949 bytes MEM: Free's : 26 free's of 12405949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.9837331681763704 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_740] 1 True 0.10
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_740'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_740', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=4022186 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cd6750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_740/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_62] 1 True 0.19
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_62'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_62', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=4022236 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00e7340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8236s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5544507828318338 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5544507828318338 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_19] 1 True 0.25
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_19'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_19', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=4022305 parent=4006011 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c75410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.21108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.21136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.21166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.21187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.21215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.21244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.21276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.21298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.21323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.21344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.21368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.21392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.21415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.21439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.21464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.21489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.21513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.21580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.21608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.21633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.21656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.21683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.21707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22099s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8577405070321126 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12333433 bytes MEM: Free's : 26 free's of 12333433 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8577405070321126 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_513] 1 True 0.32
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_513'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_513', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=4022304 parent=4006532 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5287d0940 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4859s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4861s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5197788857226195 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68980029 bytes MEM: Free's : 26 free's of 68980029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5197788857226195 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_272] 1 True 0.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_272'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_272', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=4023347 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbd64990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.19083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.19118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.19150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.19198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.19225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.19248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.19268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.19292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20128s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20131s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6648514945181219 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21372093 bytes MEM: Free's : 26 free's of 21372093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6648514945181219 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_738] 1 True 0.06
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_738'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_738', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=4023674 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3e8610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_738/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_742] 1 True 0.07
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_742'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_742', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=4023796 parent=4006962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386149f70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_742/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_33] 1 True 0.31
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_33'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_33', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=4024022 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f06fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6198s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.0429623858376147 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329981 bytes MEM: Free's : 26 free's of 12329981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.0429623858376147 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_734] 1 True 0.15
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_734'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_734', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=4024121 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3eced0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_734/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_516] 1 True 0.63
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_516'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_516', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=4024188 parent=4006014 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e93f6750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1820s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.2989852906183947 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76189293 bytes MEM: Free's : 26 free's of 76189293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.2989852906183947 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_240] 1 True 0.24
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_240'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_240', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=4024163 parent=4006168 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3057f38c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9093s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5843711376809722 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14807229 bytes MEM: Free's : 26 free's of 14807229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5843711376809722 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_437] 1 True 0.21
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_437'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_437', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=4024191 parent=4006962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386cd8b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6810179025163167 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44613085 bytes MEM: Free's : 26 free's of 44613085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6810179025163167 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_737] 1 True 0.18
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_737'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_737', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=4024234 parent=4006008 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df63f460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_737/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_65] 1 True 0.26
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_65'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_65', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=4024481 parent=4006497 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2faad640 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.0849669843631027 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328885 bytes MEM: Free's : 26 free's of 12328885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.0849669843631027 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_351] 1 True 0.55
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_351'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_351', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=4024738 parent=4006011 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c79d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.334282673578277 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 61036205 bytes MEM: Free's : 26 free's of 61036205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.334282673578277 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_14] 1 True 0.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_14'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_14', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=4025449 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4630d250 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17572s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2003466378303183 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332921 bytes MEM: Free's : 26 free's of 12332921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2003466378303183 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_165] 1 True 0.15
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_165'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_165', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=4025429 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbfb710 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17377s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.4245784431045518 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12421309 bytes MEM: Free's : 26 free's of 12421309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.4245784431045518 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_311] 1 True 0.22
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_311'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_311', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=4025589 parent=4006532 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5287d0850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1961032055778027 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25746621 bytes MEM: Free's : 26 free's of 25746621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1961032055778027 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_169] 1 True 0.24
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_169'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_169', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=4026312 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34ce1da0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1961s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.8252348293281528 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12421309 bytes MEM: Free's : 26 free's of 12421309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.8252348293281528 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_314] 1 True 0.21
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_314'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_314', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=4026460 parent=4006729 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e0cfa00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1535s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2213029686386436 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25746621 bytes MEM: Free's : 26 free's of 25746621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2213029686386436 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_395] 1 True 0.39
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_395'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_395', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=4026596 parent=4006168 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058189630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8882s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8057095441809752 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72369805 bytes MEM: Free's : 26 free's of 72369805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8057095441809752 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_747] 1 True 0.19
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_747'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_747', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=4026874 parent=4006962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386154a90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_747/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_352] 1 True 0.59
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_352'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_352', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=4027081 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebb9194d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.3425814644923206 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 55130301 bytes MEM: Free's : 26 free's of 55130301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.3425814644923206 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_203] 1 True 0.20
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_203'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_203', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=4027543 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00076a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5485s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5235739588408302 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13419709 bytes MEM: Free's : 26 free's of 13419709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5235739588408302 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_432] 1 True 0.58
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_432'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_432', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=4027616 parent=4006532 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d52963e7f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15242s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15247s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.219433714920727 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44613085 bytes MEM: Free's : 26 free's of 44613085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.219433714920727 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_159] 1 True 0.20
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_159'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_159', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=4027637 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800b62d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2746s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2748s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7254275974546351 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12405949 bytes MEM: Free's : 26 free's of 12405949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7254275974546351 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_313] 1 True 0.24
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_313'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_313', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=4028320 parent=4006011 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7ed8110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1430s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2265594882868731 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26668221 bytes MEM: Free's : 26 free's of 26668221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2265594882868731 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_128] 1 True 0.26
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_128'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_128', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=4028764 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800b8560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2056s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8298754102051403 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12370109 bytes MEM: Free's : 26 free's of 12370109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8298754102051403 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_517] 1 True 0.73
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_517'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_517', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=4029236 parent=4006295 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02acf8b30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11515s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11518s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2450439668478073 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71863101 bytes MEM: Free's : 26 free's of 71863101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2450439668478073 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_353] 1 True 0.25
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_353'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_353', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=4029204 parent=4006962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566385e94e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4090s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6003s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6004s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.338757659929308 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 55130301 bytes MEM: Free's : 26 free's of 55130301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.338757659929308 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_732] 1 True 0.07
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_732'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_732', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=4029438 parent=4006400 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1d3b90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_732/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_35] 1 True 0.35
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_35'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_35', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=4029869 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f11b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.148s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.22594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5691376458307349 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5691376458307349 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_435] 1 True 0.39
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_435'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_435', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=4029871 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebc78ad60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.2145938682403807 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44613085 bytes MEM: Free's : 26 free's of 44613085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.2145938682403807 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_716] 1 True 0.11
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_716'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_716', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=4029868 parent=4006014 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a532a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_716/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_714] 1 True 0.09
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_714'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_714', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=4030119 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00fc830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_714/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_156] 1 True 0.17
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_156'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_156', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=4030870 parent=4006168 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30584768f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.865360040242531 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12409021 bytes MEM: Free's : 26 free's of 12409021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.865360040242531 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_749] 1 True 0.12
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_749'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_749', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=4030934 parent=4006400 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1d7120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_749/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_63] 1 True 0.31
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_63'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_63', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=4031111 parent=4006008 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df646e90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.737748332920758 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329653 bytes MEM: Free's : 26 free's of 12329653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.737748332920758 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_153] 1 True 0.22
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_153'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_153', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=4030958 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34ce7d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8561121811648804 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12412093 bytes MEM: Free's : 26 free's of 12412093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8561121811648804 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_709] 1 True 0.13
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_709'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_709', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=4031894 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb01059a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_709/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_1] 1 True 0.20
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_1'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_1', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=4031870 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbffcb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8096s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.7866503893294272 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332921 bytes MEM: Free's : 26 free's of 12332921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.7866503893294272 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_168] 1 True 0.23
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_168'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_168', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=4032287 parent=4006532 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528abb850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5050116521164383 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12409021 bytes MEM: Free's : 26 free's of 12409021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5050116521164383 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_744] 1 True 0.09
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_744'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_744', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=4032204 parent=4006729 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3bd420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_744/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_705] 1 True 0.09
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_705'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_705', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=4032417 parent=4006295 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a502d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_705/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_163] 1 True 0.20
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_163'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_163', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=4032817 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb0105580 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5276639057287879 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12409021 bytes MEM: Free's : 26 free's of 12409021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5276639057287879 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_746] 1 True 0.08
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_746'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_746', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=4032821 parent=4006400 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1db7b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_746/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_731] 1 True 0.14
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_731'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_731', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=4032883 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4631c930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_731/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_232] 1 True 0.37
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_232'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_232', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=4033137 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34d2ff70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16922s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.92172183979485 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14960829 bytes MEM: Free's : 26 free's of 14960829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.92172183979485 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_312] 1 True 0.35
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_312'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_312', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=4033390 parent=4006962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5663863b52e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1923s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1925s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2353443634582213 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26668221 bytes MEM: Free's : 26 free's of 26668221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2353443634582213 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_3] 1 True 0.18
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_3'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_3', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=4033503 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800c0b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1617s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1620s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6550924113821155 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332665 bytes MEM: Free's : 26 free's of 12332665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6550924113821155 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_518] 1 True 0.51
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_518'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_518', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=4034479 parent=4006020 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea8d460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6819122211150919 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71863101 bytes MEM: Free's : 26 free's of 71863101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6819122211150919 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_708] 1 True 0.11
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_708'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_708', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=4034814 parent=4006014 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a589d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_708/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_477] 1 True 0.36
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_477'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_477', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=4034908 parent=4006396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b05c03c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1372s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.143742970468516 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33959197 bytes MEM: Free's : 26 free's of 33959197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.143742970468516 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_358] 1 True 0.49
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_358'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_358', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=4035147 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cec300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.169s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1509s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1511s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.4401990896127796 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58079421 bytes MEM: Free's : 26 free's of 58079421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.4401990896127796 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_713] 1 True 0.16
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_713'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_713', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=4035324 parent=4006014 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a5b6f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_713/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_726] 1 True 0.16
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_726'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_726', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=4035437 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3fe090 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_726/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_745] 1 True 0.11
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_745'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_745', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=4035413 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f1d9e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_745/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_704] 1 True 0.15
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_704'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_704', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=4035614 parent=4006599 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c7d0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_704/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_750] 1 True 0.09
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_750'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_750', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=4036008 parent=4006063 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004b61f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_750/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_160] 1 True 0.26
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_160'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_160', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=4036187 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f21f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13186s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7931181502805071 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12405949 bytes MEM: Free's : 26 free's of 12405949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7931181502805071 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_472] 1 True 0.26
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_472'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_472', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=4036188 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d110360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.088968411911169 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33959197 bytes MEM: Free's : 26 free's of 33959197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.088968411911169 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_720] 1 True 0.11
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_720'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_720', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=4036868 parent=4006396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08b0310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_720/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_396] 1 True 0.68
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_396'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_396', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=4037087 parent=4006962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386165cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.134s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17256s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.5207642489188533 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 74309261 bytes MEM: Free's : 26 free's of 74309261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.5207642489188533 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_288] 1 True 0.20
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_288'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_288', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=4037366 parent=4006011 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7da8e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4488s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7565717739428665 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21273789 bytes MEM: Free's : 26 free's of 21273789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7565717739428665 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_476] 1 True 0.43
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_476'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_476', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=4038238 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cafd4fa40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12890s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12893s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.566642627079865 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33432861 bytes MEM: Free's : 26 free's of 33432861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.566642627079865 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_238] 1 True 0.41
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_238'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_238', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=4038301 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a462cd150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1621s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1525655947232638 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15191229 bytes MEM: Free's : 26 free's of 15191229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1525655947232638 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_282] 1 True 0.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_282'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_282', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=4038303 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbdb0430 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1949s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.9433755451175403 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21421373 bytes MEM: Free's : 26 free's of 21421373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.9433755451175403 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_356] 1 True 0.34
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_356'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_356', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=4038346 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f72e1ab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9735s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9737s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.3494770130174576 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 55130301 bytes MEM: Free's : 26 free's of 55130301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.3494770130174576 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_320] 1 True 0.26
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_320'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_320', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=4039022 parent=4006400 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7ef0eab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2365969400076096 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25746621 bytes MEM: Free's : 26 free's of 25746621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2365969400076096 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_431] 1 True 0.25
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_431'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_431', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=4039602 parent=4006020 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e7a3a00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4870s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4872s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1362145148341005 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42023261 bytes MEM: Free's : 26 free's of 42023261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1362145148341005 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_322] 1 True 0.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_322'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_322', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=4039645 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d026820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.28153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.28189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.28229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.28252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.28277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.28300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.28328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.28348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.28383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.28409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.28435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.28458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.28479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.28505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.28530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.28554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.28577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.28598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.28619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.28641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.28665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.28693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.28713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.28739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.28760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.28782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.28805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.28826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.28846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.28866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.28895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.28919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.28940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.28962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.28990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.29011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.29037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.29058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.29082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.29111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.29140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.29142s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.29145s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5950566985601377 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25285821 bytes MEM: Free's : 26 free's of 25285821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5950566985601377 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_471] 1 True 0.32
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_471'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_471', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=4039647 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fdd8ba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5782838120290561 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33959197 bytes MEM: Free's : 26 free's of 33959197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5782838120290561 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_10] 1 True 0.22
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_10'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_10', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=4039738 parent=4006295 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a50adb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1450s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1452s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.3565082107122013 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12333305 bytes MEM: Free's : 26 free's of 12333305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.3565082107122013 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_474] 1 True 0.23
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_474'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_474', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=4040334 parent=4006827 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6c332c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6752228375908443 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33959197 bytes MEM: Free's : 26 free's of 33959197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6752228375908443 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_104] 1 True 0.21
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_104'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_104', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=4040526 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb010f950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5317s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.9596240892746908 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334549 bytes MEM: Free's : 26 free's of 12334549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.9596240892746908 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_99] 1 True 0.25
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_99'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_99', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=4041008 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbc0d2c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1500s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1501s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.6702746986635377 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12335445 bytes MEM: Free's : 26 free's of 12335445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.6702746986635377 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_327] 1 True 0.34
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_327'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_327', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=4041361 parent=4006011 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7f34220 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1746998094392669 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25516349 bytes MEM: Free's : 26 free's of 25516349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1746998094392669 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_271] 1 True 0.23
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_271'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_271', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=4041804 parent=4006400 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f363d30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4186s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1164703155515523 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21372093 bytes MEM: Free's : 26 free's of 21372093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1164703155515523 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_2] 1 True 0.23
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_2'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_2', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=4041846 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb0112270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2262s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.6402425098780602 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12333305 bytes MEM: Free's : 26 free's of 12333305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.6402425098780602 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_323] 1 True 0.24
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_323'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_323', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=4041983 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d0268e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7910854292525835 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25285821 bytes MEM: Free's : 26 free's of 25285821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7910854292525835 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_318] 1 True 0.27
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_318'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_318', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=4041981 parent=4006063 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f7000441520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1698s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1888598460282425 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27593981 bytes MEM: Free's : 26 free's of 27593981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1888598460282425 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_40] 1 True 0.21
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_40'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_40', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=4042600 parent=4006129 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172595d5f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3719s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.3855787048012644 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329981 bytes MEM: Free's : 26 free's of 12329981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.3855787048012644 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_161] 1 True 0.19
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_161'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_161', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=4042913 parent=4006295 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a513a00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3132s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3134s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.820644725932086 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12405949 bytes MEM: Free's : 26 free's of 12405949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.820644725932086 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_4] 1 True 0.16
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_4'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_4', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=4042709 parent=4006729 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3c8f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2632s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2633s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.6281943642522039 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12333305 bytes MEM: Free's : 26 free's of 12333305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.6281943642522039 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_748] 1 True 0.07
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_748'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_748', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=4042915 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb0118f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_748/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_478] 1 True 0.30
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_478'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_478', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=4043288 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a45f45570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.2789s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5581409696982128 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33432861 bytes MEM: Free's : 26 free's of 33432861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5581409696982128 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_511] 1 True 0.40
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_511'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_511', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=4043777 parent=4006063 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f7000cbf8d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1377s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.685730411186892 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71863101 bytes MEM: Free's : 26 free's of 71863101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.685730411186892 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_743] 1 True 0.07
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_743'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_743', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=4043778 parent=4006729 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3cfc10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_743/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_315] 1 True 0.37
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_315'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_315', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=4043930 parent=4006532 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528ac7a60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.34147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.34186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.34226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.34254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.34282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.34313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.34337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.34359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.34390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.34417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.34440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.34467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.34495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.34526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.34554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.34578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.34604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.34634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.34660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.34684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.34706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.34732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.34757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.34781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.34806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.34829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.34849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.34871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.34896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.34922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.34947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.34968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.34994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.35014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.35033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.35057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.35087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.35109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.35142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.35167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.35194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.35197s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.35201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2393097219986968 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26668221 bytes MEM: Free's : 26 free's of 26668221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2393097219986968 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_276] 1 True 0.28
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_276'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_276', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=4044821 parent=4006295 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a68ab60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1546s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.9646464543206409 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21372093 bytes MEM: Free's : 26 free's of 21372093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.9646464543206409 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_233] 1 True 0.23
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_233'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_233', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=4045325 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fcef230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6866157233044742 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14807229 bytes MEM: Free's : 26 free's of 14807229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6866157233044742 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_7] 1 True 0.15
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_7'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_7', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=4045353 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cf7870 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6726982603032365 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332921 bytes MEM: Free's : 26 free's of 12332921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6726982603032365 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_278] 1 True 0.37
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_278'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_278', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=4045923 parent=4006729 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e549aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17706s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.9948637501962002 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21372093 bytes MEM: Free's : 26 free's of 21372093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.9948637501962002 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_701] 1 True 0.15
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_701'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_701', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=4045964 parent=4006396 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08c09e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_701/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_439] 1 True 0.38
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_439'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_439', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=4045965 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4603f950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9488s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9490s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6783991542958426 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42023261 bytes MEM: Free's : 26 free's of 42023261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6783991542958426 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_91] 1 True 0.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_91'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_91', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=4045967 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbc17720 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.682913991139302 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12336853 bytes MEM: Free's : 26 free's of 12336853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.682913991139302 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_194] 1 True 0.25
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_194'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_194', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=4046653 parent=4006295 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a42d060 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4904s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4905s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.6462602216937781 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13419709 bytes MEM: Free's : 26 free's of 13419709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.6462602216937781 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_473] 1 True 0.27
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_473'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_473', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=4047072 parent=4006164 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cafe393b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1417s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.0661500790463605 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33959197 bytes MEM: Free's : 26 free's of 33959197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.0661500790463605 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_236] 1 True 0.24
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_236'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_236', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=4047318 parent=4006962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566385e0b2e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12013s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8206675476781112 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14884029 bytes MEM: Free's : 26 free's of 14884029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8206675476781112 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_397] 1 True 1.02
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_397'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_397', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=4047453 parent=4006024 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebc01b690 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1432s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.2376736642725543 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 87896101 bytes MEM: Free's : 26 free's of 87896101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.2376736642725543 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_400] 1 True 0.64
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_400'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_400', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=4047736 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cfb330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.21057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.21079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.21107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.21131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.21149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.21169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7433743593370301 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72369805 bytes MEM: Free's : 26 free's of 72369805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7433743593370301 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_319] 1 True 0.40
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_319'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_319', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=4048318 parent=4006400 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1f5550 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1958s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.089725475690727 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26668221 bytes MEM: Free's : 26 free's of 26668221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.089725475690727 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_733] 1 True 0.09
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_733'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_733', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=4048476 parent=4006295 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a521020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_733/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_277] 1 True 0.20
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_277'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_277', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=4048475 parent=4006020 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e7a8d30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1590s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.1417912148141225 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22158525 bytes MEM: Free's : 26 free's of 22158525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.1417912148141225 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_715] 1 True 0.20
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_715'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_715', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=4048598 parent=4006861 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800dbdf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_715/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_237] 1 True 0.17
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_237'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_237', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=4048714 parent=4006497 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f6ed430 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1454s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1456s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1391723862118983 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15037629 bytes MEM: Free's : 26 free's of 15037629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1391723862118983 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_719] 1 True 0.11
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_719'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_719', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=4048778 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a463379e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_719/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_739] 1 True 0.13
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_739'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_739', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=4049079 parent=4006008 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df664b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_739/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_68] 1 True 0.25
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_68'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_68', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=4049411 parent=4006330 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cda7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1911s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.7718688806059804 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.7718688806059804 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_482] 1 True 0.33
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_482'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_482', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=4050162 parent=4006011 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f78da3a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.5027595650554858 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33432861 bytes MEM: Free's : 26 free's of 33432861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.5027595650554858 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_170] 1 True 0.23
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_170'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_170', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=4050357 parent=4006295 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a528760 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5740s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5743s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.8294085580641068 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12415165 bytes MEM: Free's : 26 free's of 12415165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.8294085580641068 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_722] 1 True 0.10
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_722'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_722', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=4050515 parent=4006962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638617b8c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_722/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_520] 1 True 0.41
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_520'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_520', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=4050546 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d415b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1595s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.9781527578966575 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71863101 bytes MEM: Free's : 26 free's of 71863101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.9781527578966575 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_718] 1 True 0.16
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_718'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_718', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=4050600 parent=4006729 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3dee80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_718/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_480] 1 True 0.29
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_480'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_480', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=4050650 parent=4006330 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cdc6c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4822s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4824s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.1200464658160267 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34485661 bytes MEM: Free's : 26 free's of 34485661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.1200464658160267 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_195] 1 True 0.28
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_195'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_195', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=4050699 parent=4006014 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7987fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6755s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6757s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8676877247854813 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13419709 bytes MEM: Free's : 26 free's of 13419709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8676877247854813 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_391] 1 True 0.49
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_391'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_391', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=4050723 parent=4006897 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a350fefe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1248s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.8664315787691229 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 82068669 bytes MEM: Free's : 26 free's of 82068669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 0.8664315787691229 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_360] 1 True 0.21
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_360'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_360', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=4051613 parent=4006017 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a466fa000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.4932778366814667 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 55130301 bytes MEM: Free's : 26 free's of 55130301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.4932778366814667 is higher than threshold 0.5
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_730] 1 True 0.08
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_730'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_730', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=4051767 parent=4006497 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fadfb60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/ScatterND_730/artifacts/subgraph_0_tidl_net.bin
------------------------------Captured stderr call------------------------------
Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1
Failed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_434] 1 True 0.15
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'ScatterND_434'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = True, test_name = 'ScatterND_434', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/ScatterND'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=4052160 parent=4006028 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7dfa9bf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 2.2024895785413823 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 44613085 bytes MEM: Free's : 26 free's of 44613085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 2.2024895785413823 is higher than threshold 0.5
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_302] 1 True 0.23
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c1eb20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.30178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.30205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.30222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.30237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.30261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.30276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.30293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.30310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.30324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.30340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.30357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.30372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.30385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.30408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.30426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.30452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.30472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.30488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.30504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.30521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.30536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.30553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.30570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.30584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.30600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.30619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.30633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.30647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.30663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.30674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.30690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.30705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.30718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.30730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.30746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.30758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.30777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.30866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.30882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.30898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.30921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.30922s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.30925s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002115431298594354 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.37 Core Time (ms) : 21.89 TIDL Subgraphs Processing Time (ms) : 21.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979133 bytes MEM: Free's : 26 free's of 20979133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_55] 1 True 0.28
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a495830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.48907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.48944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.48971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.48996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.49026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.49050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.49076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.49096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.49123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.49145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.49172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.49194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.49219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.49246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.49272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.49298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.49321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.49339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.49364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.49392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.49416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.49441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.49468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.49491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.49517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.49557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.49576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.49595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.49621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.49640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.49667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.49690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.49714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.49734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.49760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.49780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.49807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.49835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.49854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.49881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.49909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.49911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.49914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03695607194753837 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.64 Core Time (ms) : 14.61 TIDL Subgraphs Processing Time (ms) : 14.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_556] 0 - 0.19
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3057f38c20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_402] 1 True 0.28
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725578340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1498085251468311 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.11 Core Time (ms) : 32.81 TIDL Subgraphs Processing Time (ms) : 32.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70877965 bytes MEM: Free's : 26 free's of 70877965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_427] 1 True 0.65
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00936c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6499s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02402554074062529 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 121.06 Core Time (ms) : 117.88 TIDL Subgraphs Processing Time (ms) : 117.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395237 bytes MEM: Free's : 26 free's of 72395237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_77] 1 True 0.21
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fa51180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01634469317815435 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.79 Core Time (ms) : 3.78 TIDL Subgraphs Processing Time (ms) : 3.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_623] 0 - 0.16
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187eb37f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_242] 1 True 0.30
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6dc36b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.33509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.33594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.33634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.33658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.33688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.33709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.33730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.33755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.33778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.33797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.33827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.33852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.33875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.33900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.33921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.33946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.33974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.33992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.34016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.34040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.34060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.34086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.34114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.34137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.34160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.34183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.34204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.34228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.34251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.34271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.34289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.34312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.34331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.34358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.34382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.34400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.34424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.34463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.34468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.34471s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.14381427920334613 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.67 Core Time (ms) : 46.47 TIDL Subgraphs Processing Time (ms) : 46.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14749629 bytes MEM: Free's : 26 free's of 14749629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_537] 1 True 0.42
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e34e490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.26715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.26753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.26787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.26811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.26844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.26867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.26893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.26913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.26935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.26955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.26985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.27006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.27029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.27055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.27076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.27099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.27123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.27148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.27171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.27192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27749s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27751s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06985762473940807 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.97 Core Time (ms) : 43.45 TIDL Subgraphs Processing Time (ms) : 43.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67539901 bytes MEM: Free's : 26 free's of 67539901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_523] 1 True 0.34
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7661060 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.14141293783557016 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.30 Core Time (ms) : 47.21 TIDL Subgraphs Processing Time (ms) : 47.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67931709 bytes MEM: Free's : 26 free's of 67931709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_508] 1 True 0.29
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3c5f730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.131s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12075890083148233 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 42.60 Core Time (ms) : 41.42 TIDL Subgraphs Processing Time (ms) : 41.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906653 bytes MEM: Free's : 26 free's of 32906653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_539] 1 True 0.31
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d380730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02726946751063522 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 109.83 Core Time (ms) : 106.21 TIDL Subgraphs Processing Time (ms) : 106.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67539901 bytes MEM: Free's : 26 free's of 67539901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_611] 0 - 0.13
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbb93260 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_366] 1 True 0.27
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f7000293f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8063s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.35520700184943493 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.07 Core Time (ms) : 31.25 TIDL Subgraphs Processing Time (ms) : 31.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52771005 bytes MEM: Free's : 26 free's of 52771005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_119] 1 True 0.29
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34c77bd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1456s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012647715953786522 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.69 Core Time (ms) : 2.67 TIDL Subgraphs Processing Time (ms) : 2.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_833] 0 - 0.17
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b0852a00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_755] 0 - 0.17
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c17dc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_663] 0 - 0.15
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea21590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.55 Core Time (ms) : 0.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_390] 1 True 0.22
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df5e2560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1671s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00448534253886546 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.87 Core Time (ms) : 19.91 TIDL Subgraphs Processing Time (ms) : 19.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_201] 1 True 0.17
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbaaab10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.21736978605703544 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.04 Core Time (ms) : 0.97 TIDL Subgraphs Processing Time (ms) : 0.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13382845 bytes MEM: Free's : 26 free's of 13382845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_138] 1 True 0.23
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea26350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1529s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1532s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11196941446236779 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_612] 0 - 0.10
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c1dd30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_252] 1 True 0.24
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f7000355f10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07982658808355463 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.09 Core Time (ms) : 24.92 TIDL Subgraphs Processing Time (ms) : 24.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14731453 bytes MEM: Free's : 26 free's of 14731453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_251] 1 True 0.28
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60b2a7d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11883491416976083 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.78 Core Time (ms) : 10.59 TIDL Subgraphs Processing Time (ms) : 10.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14731197 bytes MEM: Free's : 26 free's of 14731197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_454] 1 True 0.24
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a49aa00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1722s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1724s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.021678937722527797 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 49.74 Core Time (ms) : 48.29 TIDL Subgraphs Processing Time (ms) : 48.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40730845 bytes MEM: Free's : 26 free's of 40730845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_862] 0 - 0.22
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b39c6ae0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_414] 1 True 0.49
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6eab660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4488s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.2888834984401486 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 95.88 Core Time (ms) : 92.85 TIDL Subgraphs Processing Time (ms) : 92.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72396389 bytes MEM: Free's : 26 free's of 72396389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_679] 0 - 0.20
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbb95130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.09 Core Time (ms) : 11.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_6] 1 True 0.19
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3848d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4431622170744116 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.11 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332921 bytes MEM: Free's : 26 free's of 12332921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_285] 1 True 0.23
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a6f3e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.36588688560436855 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.27 Core Time (ms) : 12.05 TIDL Subgraphs Processing Time (ms) : 11.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21126333 bytes MEM: Free's : 26 free's of 21126333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_596] 0 - 0.09
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a461fbfc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_856] 0 - 0.12
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea43c90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_693] 0 - 0.09
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a8c760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_324] 1 True 0.15
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a45e76700 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1768s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001058082143334566 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.66 Core Time (ms) : 8.33 TIDL Subgraphs Processing Time (ms) : 8.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24901821 bytes MEM: Free's : 26 free's of 24901821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_610] 0 - 0.07
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a4280467330 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0.45256592992189953 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_810] 0 - 0.12
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f700035cf10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_446] 1 True 0.18
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3814d00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1368s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0088744243401384 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.88 Core Time (ms) : 14.49 TIDL Subgraphs Processing Time (ms) : 14.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40872157 bytes MEM: Free's : 26 free's of 40872157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_831] 0 - 0.09
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbb1930 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_90] 1 True 0.16
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a49d5a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004729402657111677 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.57 Core Time (ms) : 6.55 TIDL Subgraphs Processing Time (ms) : 6.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328885 bytes MEM: Free's : 26 free's of 12328885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_36] 1 True 0.17
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a8ee60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.35627841873366045 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.74 Core Time (ms) : 3.71 TIDL Subgraphs Processing Time (ms) : 3.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_681] 0 - 0.13
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800923e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.61 Core Time (ms) : 0.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_368] 1 True 0.48
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60792e60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10974s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.039570193868084656 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.11 Core Time (ms) : 45.05 TIDL Subgraphs Processing Time (ms) : 44.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52377789 bytes MEM: Free's : 26 free's of 52377789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_769] 0 - 0.08
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e79ed7a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_800] 0 - 0.07
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbb97f50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_756] 0 - 0.06
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f7000447960 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_804] 0 - 0.09
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615caffb2b50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_346] 1 True 0.19
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b087bfc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4732s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06782315377684986 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.85 Core Time (ms) : 5.26 TIDL Subgraphs Processing Time (ms) : 5.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_79] 1 True 0.21
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e79ec510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00014737856642392188 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.13 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_76] 1 True 0.17
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a4280094c30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2522s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0745230299261865 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.78 Core Time (ms) : 1.76 TIDL Subgraphs Processing Time (ms) : 1.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_915] 0 - 0.13
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a3b4cc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.30 Core Time (ms) : 0.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_362] 1 True 0.27
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebb8cbad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011983994291083043 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.90 Core Time (ms) : 37.11 TIDL Subgraphs Processing Time (ms) : 37.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52377789 bytes MEM: Free's : 26 free's of 52377789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_490] 1 True 0.37
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f6ffff69330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0015586368227943875 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 68.83 Core Time (ms) : 67.58 TIDL Subgraphs Processing Time (ms) : 67.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32994205 bytes MEM: Free's : 26 free's of 32994205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_622] 0 - 0.13
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3e4cb70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_700] 0 - 0.11
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a900d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.63 Core Time (ms) : 0.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_664] 0 - 0.08
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058442e60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_335] 1 True 0.29
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb0098180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1857s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1860s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008554182104915337 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.74 Core Time (ms) : 8.94 TIDL Subgraphs Processing Time (ms) : 8.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24826045 bytes MEM: Free's : 26 free's of 24826045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_669] 0 - 0.08
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1ac7c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.01 Core Time (ms) : 1.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_822] 0 - 0.06
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e981440 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_485] 1 True 0.34
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d078ab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21204s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21207s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.18104057675296475 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.77 Core Time (ms) : 30.58 TIDL Subgraphs Processing Time (ms) : 30.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33081885 bytes MEM: Free's : 26 free's of 33081885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_12] 1 True 0.19
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e394c30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1458s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1460s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.019336928742022086 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.18 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332665 bytes MEM: Free's : 26 free's of 12332665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_609] 0 - 0.17
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6b59c70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_754] 0 - 0.19
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cc3130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_142] 1 True 0.23
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea6c690 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2921s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2924s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011323068201526613 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.05 Core Time (ms) : 4.04 TIDL Subgraphs Processing Time (ms) : 4.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_828] 0 - 0.10
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638604d900 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_767] 0 - 0.23
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a94c20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_581] 0 - 0.17
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a3b54c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_778] 0 - 0.10
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1b10a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_342] 1 True 0.29
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3c66a50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1785s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1787s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01686301315580584 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.66 Core Time (ms) : 10.07 TIDL Subgraphs Processing Time (ms) : 10.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_283] 1 True 0.27
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b087d890 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2696s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12139363301202435 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.06 Core Time (ms) : 7.51 TIDL Subgraphs Processing Time (ms) : 7.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21028029 bytes MEM: Free's : 26 free's of 21028029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_502] 1 True 0.22
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e79eddd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11407236986974045 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.06 Core Time (ms) : 11.86 TIDL Subgraphs Processing Time (ms) : 11.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906653 bytes MEM: Free's : 26 free's of 32906653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_642] 0 - 0.22
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df80c7e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_82] 1 True 0.22
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187ef9840 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17298s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.09589435612614766 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.64 Core Time (ms) : 21.62 TIDL Subgraphs Processing Time (ms) : 21.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_788] 0 - 0.11
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c67fb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_268] 1 True 0.29
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638604b350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.34206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.34291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.34314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.34358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.34381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.34408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.34430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.34454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.34478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.34498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.34521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.34544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.34571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.34592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.34613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.34638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.34659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.34682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.34705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.34725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.34749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.34774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.34795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.34814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.34836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.34862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.34882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.34907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.34931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.34955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.34976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.35000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.35026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.35046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.35070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.35096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.35118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.35146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.35172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.35200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.35205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.35208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.14607779449764766 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.65 Core Time (ms) : 1.45 TIDL Subgraphs Processing Time (ms) : 1.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_662] 0 - 0.12
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebb8cbb50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_338] 1 True 0.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058447b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6155s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05342615085885027 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.17 Core Time (ms) : 18.56 TIDL Subgraphs Processing Time (ms) : 18.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24826045 bytes MEM: Free's : 26 free's of 24826045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_577] 0 - 0.12
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6dc4be0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_413] 1 True 0.59
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e396f20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5495s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3204287991456976 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 108.40 Core Time (ms) : 96.33 TIDL Subgraphs Processing Time (ms) : 96.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72396389 bytes MEM: Free's : 26 free's of 72396389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_381] 1 True 0.21
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4a0940 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05760684143100119 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.96 Core Time (ms) : 47.27 TIDL Subgraphs Processing Time (ms) : 47.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_624] 0 - 0.11
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a462f6ab0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_453] 1 True 0.28
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c67440 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.10898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11831s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11833s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04634170322653485 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 42.08 Core Time (ms) : 40.33 TIDL Subgraphs Processing Time (ms) : 40.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728925 bytes MEM: Free's : 26 free's of 40728925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_423] 1 True 0.40
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c19db0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0045129961100534785 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 95.66 Core Time (ms) : 92.16 TIDL Subgraphs Processing Time (ms) : 92.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395365 bytes MEM: Free's : 26 free's of 72395365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_907] 0 - 0.16
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5289a8470 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.40 Core Time (ms) : 1.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_284] 1 True 0.21
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5917259b6dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4440231648749847 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.80 Core Time (ms) : 5.60 TIDL Subgraphs Processing Time (ms) : 5.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21126333 bytes MEM: Free's : 26 free's of 21126333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_182] 1 True 0.14
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6eb3cc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.021320457133060453 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403261 bytes MEM: Free's : 26 free's of 12403261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_98] 1 True 0.24
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3cc010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 5.447482230352038e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.26 Core Time (ms) : 2.25 TIDL Subgraphs Processing Time (ms) : 2.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334677 bytes MEM: Free's : 26 free's of 12334677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_257] 1 True 0.37
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df53f980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19119s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08844475842267083 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.71 Core Time (ms) : 16.52 TIDL Subgraphs Processing Time (ms) : 16.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730813 bytes MEM: Free's : 26 free's of 14730813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_112] 1 True 0.26
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a462f5000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03554589830495785 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_451] 1 True 0.26
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b087fad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0011442005412305096 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.04 Core Time (ms) : 22.46 TIDL Subgraphs Processing Time (ms) : 22.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728925 bytes MEM: Free's : 26 free's of 40728925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_889] 0 - 0.19
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3e241f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_586] 0 - 0.19
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9b2290 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_901] 0 - 0.13
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058360920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_496] 1 True 0.24
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea71a30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4412s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4414s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0301017087921325 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.28 Core Time (ms) : 15.69 TIDL Subgraphs Processing Time (ms) : 15.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32911389 bytes MEM: Free's : 26 free's of 32911389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_217] 1 True 0.27
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a3b82b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08570925076140656 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.66 Core Time (ms) : 14.56 TIDL Subgraphs Processing Time (ms) : 14.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_566] 0 - 0.13
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386052cc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_492] 1 True 0.25
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1b3ab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.010780260209287247 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.54 Core Time (ms) : 24.35 TIDL Subgraphs Processing Time (ms) : 24.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32907037 bytes MEM: Free's : 26 free's of 32907037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_263] 1 True 0.19
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7b7e2e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1697s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12325024692481805 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.44 Core Time (ms) : 1.31 TIDL Subgraphs Processing Time (ms) : 1.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_536] 1 True 0.54
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f305844d380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24627s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.017991561197933957 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 158.00 Core Time (ms) : 151.57 TIDL Subgraphs Processing Time (ms) : 151.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67540413 bytes MEM: Free's : 26 free's of 67540413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_544] 1 True 0.39
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5663861385d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4030s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003186326299389536 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.34 Core Time (ms) : 47.48 TIDL Subgraphs Processing Time (ms) : 47.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538749 bytes MEM: Free's : 26 free's of 67538749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_255] 1 True 0.18
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d2e39d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03412305614099346 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.92 Core Time (ms) : 4.79 TIDL Subgraphs Processing Time (ms) : 4.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14731197 bytes MEM: Free's : 26 free's of 14731197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_258] 1 True 0.15
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f700039f790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9496s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03474771026809896 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.44 Core Time (ms) : 1.32 TIDL Subgraphs Processing Time (ms) : 1.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730813 bytes MEM: Free's : 26 free's of 14730813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_293] 1 True 0.20
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f00050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1174465161589981 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.76 Core Time (ms) : 13.29 TIDL Subgraphs Processing Time (ms) : 13.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979261 bytes MEM: Free's : 26 free's of 20979261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_57] 1 True 0.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fa9cf20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14449s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04615617238261516 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.00 Core Time (ms) : 5.98 TIDL Subgraphs Processing Time (ms) : 5.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_659] 0 - 0.16
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a45f455f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_350] 1 True 0.24
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbd8e00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00419007594998808 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.62 Core Time (ms) : 27.05 TIDL Subgraphs Processing Time (ms) : 26.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_682] 0 - 0.19
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea71ca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.63 Core Time (ms) : 2.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_876] 0 - 0.14
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60d0a830 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_799] 0 - 0.14
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a35ba0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_460] 1 True 0.23
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1b78c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1970s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004291499238709247 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.05 Core Time (ms) : 25.50 TIDL Subgraphs Processing Time (ms) : 25.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40732381 bytes MEM: Free's : 26 free's of 40732381 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_388] 1 True 0.29
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4a4880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04745084052023606 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.36 Core Time (ms) : 46.65 TIDL Subgraphs Processing Time (ms) : 46.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_220] 1 True 0.31
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df542230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1992s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1994s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11625355212161609 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.29 Core Time (ms) : 6.22 TIDL Subgraphs Processing Time (ms) : 6.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_615] 0 - 0.14
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172593fbf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.39 Core Time (ms) : 10.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_678] 0 - 0.14
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f700048c450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.81 Core Time (ms) : 0.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_772] 0 - 0.15
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c6db20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_775] 0 - 0.08
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a462fa7a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_692] 0 - 0.23
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00dceb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_673] 0 - 0.20
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f03080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_639] 0 - 0.13
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34eacde0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_444] 1 True 0.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e76e5070 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1834759786535427 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.31 Core Time (ms) : 32.52 TIDL Subgraphs Processing Time (ms) : 32.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40872157 bytes MEM: Free's : 26 free's of 40872157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_854] 0 - 0.10
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbf9c60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_214] 1 True 0.19
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4620fa60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.09155110028826394 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.43 Core Time (ms) : 11.32 TIDL Subgraphs Processing Time (ms) : 11.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370941 bytes MEM: Free's : 26 free's of 13370941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_557] 0 - 0.10
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e59a250 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_546] 1 True 0.37
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a999d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12690s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12694s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.026905787179453047 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.06 Core Time (ms) : 50.37 TIDL Subgraphs Processing Time (ms) : 50.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538749 bytes MEM: Free's : 26 free's of 67538749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_206] 1 True 0.35
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725853e70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.22465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.22524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.22546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.22572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.22592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.22619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.22784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.22806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.22829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.22852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.22875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.22963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.22986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23556s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.49734514259759705 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.33 Core Time (ms) : 3.24 TIDL Subgraphs Processing Time (ms) : 3.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13395133 bytes MEM: Free's : 26 free's of 13395133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_898] 0 - 0.12
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70003a24c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_851] 0 - 0.14
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08a3170 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_547] 1 True 0.59
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c6bd70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2144s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00790717160364275 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 42.90 Core Time (ms) : 39.28 TIDL Subgraphs Processing Time (ms) : 39.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538877 bytes MEM: Free's : 26 free's of 67538877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_386] 1 True 0.30
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a428009ead0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8617s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03897800268816357 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.86 Core Time (ms) : 36.20 TIDL Subgraphs Processing Time (ms) : 36.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_593] 0 - 0.10
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d2ea150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_428] 1 True 0.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fa9f340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23975s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.033718826341878505 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 75.73 Core Time (ms) : 67.93 TIDL Subgraphs Processing Time (ms) : 67.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395237 bytes MEM: Free's : 26 free's of 72395237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_226] 1 True 0.22
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f0cdbf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3268s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.14621366649188605 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.14 Core Time (ms) : 8.05 TIDL Subgraphs Processing Time (ms) : 8.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_608] 0 - 0.14
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a349f9710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_75] 1 True 0.25
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbded40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1791s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1793s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03415449047035984 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.70 Core Time (ms) : 1.68 TIDL Subgraphs Processing Time (ms) : 1.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_409] 1 True 0.37
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e719fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05396049717573945 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.74 Core Time (ms) : 32.33 TIDL Subgraphs Processing Time (ms) : 32.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70579597 bytes MEM: Free's : 26 free's of 70579597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_576] 0 - 0.13
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3bc3b10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_877] 0 - 0.16
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4ded1190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_207] 1 True 0.34
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386055020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17981s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17983s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.20148074608960223 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.80 Core Time (ms) : 11.73 TIDL Subgraphs Processing Time (ms) : 11.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13382845 bytes MEM: Free's : 26 free's of 13382845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_841] 0 - 0.10
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4c3a50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_776] 0 - 0.12
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00e2380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_827] 0 - 0.10
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004ab340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_88] 1 True 0.31
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df630880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.28192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.28212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.28235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.28262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.28285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.28312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.28345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.28347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.28353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03777885489924707 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.21 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_871] 0 - 0.08
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a45fa5680 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_793] 0 - 0.12
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3d8c30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_448] 1 True 0.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b0536fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8189s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.030945246383008867 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 61.04 Core Time (ms) : 59.45 TIDL Subgraphs Processing Time (ms) : 59.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40872157 bytes MEM: Free's : 26 free's of 40872157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_172] 1 True 0.21
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34ccf6e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1899s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12210771586142029 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.22 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403261 bytes MEM: Free's : 26 free's of 12403261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_806] 0 - 0.12
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30583653e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_106] 1 True 0.23
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4a7cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1429s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03852224702470027 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334293 bytes MEM: Free's : 26 free's of 12334293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_204] 1 True 0.16
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7955450 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11812s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11816s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.40373603462215346 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.89 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13395133 bytes MEM: Free's : 26 free's of 13395133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_249] 1 True 0.20
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3bca8f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.14123750166884738 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.18 Core Time (ms) : 5.03 TIDL Subgraphs Processing Time (ms) : 4.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14749629 bytes MEM: Free's : 26 free's of 14749629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_884] 0 - 0.19
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb029aa00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.46 Core Time (ms) : 2.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_218] 1 True 0.20
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e2b3000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7126s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7129s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.026053452824193052 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.84 Core Time (ms) : 3.76 TIDL Subgraphs Processing Time (ms) : 3.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13371325 bytes MEM: Free's : 26 free's of 13371325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_410] 1 True 0.56
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60908ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8407s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07737931864278487 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 94.76 Core Time (ms) : 90.23 TIDL Subgraphs Processing Time (ms) : 90.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70579597 bytes MEM: Free's : 26 free's of 70579597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_221] 1 True 0.20
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f0cfee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.13659667071069245 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.71 Core Time (ms) : 0.65 TIDL Subgraphs Processing Time (ms) : 0.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_442] 1 True 0.32
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d102590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.38076999525259997 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 42.83 Core Time (ms) : 41.36 TIDL Subgraphs Processing Time (ms) : 41.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41591645 bytes MEM: Free's : 26 free's of 41591645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_455] 1 True 0.22
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800a12f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.6795s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8056s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07324534532147242 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.88 Core Time (ms) : 36.74 TIDL Subgraphs Processing Time (ms) : 36.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728925 bytes MEM: Free's : 26 free's of 40728925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_37] 1 True 0.17
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbe03b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.2392580838897186 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.11 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329341 bytes MEM: Free's : 26 free's of 12329341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_506] 1 True 0.25
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a9c0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05773708741643609 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.62 Core Time (ms) : 14.30 TIDL Subgraphs Processing Time (ms) : 14.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906781 bytes MEM: Free's : 26 free's of 32906781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_137] 1 True 0.24
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30584517d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12375799388316443 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.26 Core Time (ms) : 0.24 TIDL Subgraphs Processing Time (ms) : 0.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_369] 1 True 0.26
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5917255783f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1499s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1501s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.254807413044273 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.71 Core Time (ms) : 17.04 TIDL Subgraphs Processing Time (ms) : 16.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52771005 bytes MEM: Free's : 26 free's of 52771005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_225] 1 True 0.25
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e794fb20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.14658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15697s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15700s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10935472570963574 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.99 Core Time (ms) : 3.91 TIDL Subgraphs Processing Time (ms) : 3.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_190] 1 True 0.20
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004958e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1652s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004875502754012595 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.84 Core Time (ms) : 6.82 TIDL Subgraphs Processing Time (ms) : 6.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403517 bytes MEM: Free's : 26 free's of 12403517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_411] 1 True 0.40
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00e1ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16630s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.28419996499420996 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 61.64 Core Time (ms) : 58.22 TIDL Subgraphs Processing Time (ms) : 58.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72397669 bytes MEM: Free's : 26 free's of 72397669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_658] 0 - 0.16
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a3490fd30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_867] 0 - 0.23
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b39dd5e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_71] 1 True 0.28
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638613d790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2068s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2070s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3268665042852754 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.15 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328885 bytes MEM: Free's : 26 free's of 12328885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_92] 1 True 0.27
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3a04a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1580s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1582s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 3.983508258753464e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.75 Core Time (ms) : 14.73 TIDL Subgraphs Processing Time (ms) : 14.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334677 bytes MEM: Free's : 26 free's of 12334677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_920] 0 - 0.22
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df547bc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.33 Core Time (ms) : 0.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_291] 1 True 0.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f07dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16996s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05556974241244332 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.17 Core Time (ms) : 15.52 TIDL Subgraphs Processing Time (ms) : 15.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979261 bytes MEM: Free's : 26 free's of 20979261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_848] 0 - 0.11
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f1ac50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_228] 1 True 0.19
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f0d2280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1784s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1787s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.15455880171330705 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.03 Core Time (ms) : 4.96 TIDL Subgraphs Processing Time (ms) : 4.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_134] 1 True 0.21
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800a5820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.09442715447022976 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_20] 1 True 0.21
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c6eeb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1515s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 3.0446181419643027e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.82 Core Time (ms) : 2.81 TIDL Subgraphs Processing Time (ms) : 2.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12333305 bytes MEM: Free's : 26 free's of 12333305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_187] 1 True 0.26
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528aa2500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2024s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2026s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10503492640591444 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403517 bytes MEM: Free's : 26 free's of 12403517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_406] 1 True 0.33
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a349f9650 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2556s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.40232957313151485 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 55.15 Core Time (ms) : 51.25 TIDL Subgraphs Processing Time (ms) : 51.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 71773197 bytes MEM: Free's : 26 free's of 71773197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_93] 1 True 0.23
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3d9170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.0546448701491674e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.32 Core Time (ms) : 4.29 TIDL Subgraphs Processing Time (ms) : 4.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334677 bytes MEM: Free's : 26 free's of 12334677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_846] 0 - 0.15
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004b0d40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_28] 1 True 0.34
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a3bde0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13277s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08245686400782974 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.26 Core Time (ms) : 2.24 TIDL Subgraphs Processing Time (ms) : 2.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332537 bytes MEM: Free's : 26 free's of 12332537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_753] 0 - 0.17
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172593e310 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_900] 0 - 0.19
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46214ff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_656] 0 - 0.17
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f6e8a60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_792] 0 - 0.24
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cb4240 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_105] 1 True 0.24
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1bf6a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2234s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.010378580842865179 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.20 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334293 bytes MEM: Free's : 26 free's of 12334293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_367] 1 True 0.43
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df35f100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14917s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0008536984729532324 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.20 Core Time (ms) : 32.86 TIDL Subgraphs Processing Time (ms) : 32.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52377789 bytes MEM: Free's : 26 free's of 52377789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_11] 1 True 0.24
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbbe6300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04834944650198506 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.15 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332665 bytes MEM: Free's : 26 free's of 12332665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_464] 1 True 0.19
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638613e7a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1384s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12433047161291723 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.43 Core Time (ms) : 24.85 TIDL Subgraphs Processing Time (ms) : 24.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728413 bytes MEM: Free's : 26 free's of 40728413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_802] 0 - 0.23
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e2c0040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_644] 0 - 0.09
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a4280289790 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_768] 0 - 0.08
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f03600 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_583] 0 - 0.07
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187e1f3b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.53 Core Time (ms) : 0.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_821] 0 - 0.07
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a405180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_815] 0 - 0.07
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725858030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_461] 1 True 0.35
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c70300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007341651494211008 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 80.66 Core Time (ms) : 79.22 TIDL Subgraphs Processing Time (ms) : 79.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728413 bytes MEM: Free's : 26 free's of 40728413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_197] 1 True 0.38
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9c49a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14111s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.42093596881696177 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.66 Core Time (ms) : 7.58 TIDL Subgraphs Processing Time (ms) : 7.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13395133 bytes MEM: Free's : 26 free's of 13395133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_101] 1 True 0.21
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c61e40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2031s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06195764898594863 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.13 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_387] 1 True 0.37
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea7b160 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.30173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.30211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.30242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.30266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.30290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.30309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.30337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.30360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.30381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.30406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.30434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.30437s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.30442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008236419913173284 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 49.85 Core Time (ms) : 48.05 TIDL Subgraphs Processing Time (ms) : 47.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_13] 1 True 0.33
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00e4020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.25011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.25029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.25053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25213s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25216s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04102173493650421 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.78 Core Time (ms) : 3.76 TIDL Subgraphs Processing Time (ms) : 3.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332921 bytes MEM: Free's : 26 free's of 12332921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_64] 1 True 0.24
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f0b1e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15368s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15371s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08243393277571752 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.91 Core Time (ms) : 1.89 TIDL Subgraphs Processing Time (ms) : 1.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_54] 1 True 0.27
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f01390 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001231159123593991 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.13 Core Time (ms) : 4.11 TIDL Subgraphs Processing Time (ms) : 4.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_465] 1 True 0.53
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528a9ff40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14836s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0344983455556557 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 79.98 Core Time (ms) : 78.47 TIDL Subgraphs Processing Time (ms) : 78.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728413 bytes MEM: Free's : 26 free's of 40728413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_613] 0 - 0.16
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4f6590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_645] 0 - 0.10
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725b1ee80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_677] 0 - 0.13
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386148140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.54 Core Time (ms) : 0.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_294] 1 True 0.23
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cb2620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2780s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2782s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.058252112343475576 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.55 Core Time (ms) : 11.09 TIDL Subgraphs Processing Time (ms) : 11.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979261 bytes MEM: Free's : 26 free's of 20979261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_403] 1 True 0.41
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a349702f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05290441395786837 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 60.20 Core Time (ms) : 54.71 TIDL Subgraphs Processing Time (ms) : 54.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70579597 bytes MEM: Free's : 26 free's of 70579597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_638] 0 - 0.24
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e587380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.57 Core Time (ms) : 0.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_558] 0 - 0.14
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a196ec0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_894] 0 - 0.12
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5663860572c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.30 Core Time (ms) : 0.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_785] 0 - 0.15
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c66950 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_686] 0 - 0.12
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3de2c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.72 Core Time (ms) : 0.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_344] 1 True 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f0b6c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1467s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05540958809505796 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.20 Core Time (ms) : 16.45 TIDL Subgraphs Processing Time (ms) : 16.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_646] 0 - 0.11
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f700067d380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_757] 0 - 0.13
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df637cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_532] 1 True 0.41
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f04290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06567825711785485 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 89.66 Core Time (ms) : 86.36 TIDL Subgraphs Processing Time (ms) : 86.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67539901 bytes MEM: Free's : 26 free's of 67539901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_215] 1 True 0.26
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3bca4a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.26378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.26424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.26445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.26473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.26492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.26514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.26537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.26566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.26587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.26610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.26637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.26659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.26661s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.26667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04230017623172928 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.93 Core Time (ms) : 0.85 TIDL Subgraphs Processing Time (ms) : 0.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13371197 bytes MEM: Free's : 26 free's of 13371197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_842] 0 - 0.17
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb01025e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_636] 0 - 0.20
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7e56820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_250] 1 True 0.35
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a40af20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.14494896018122613 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.84 Core Time (ms) : 12.69 TIDL Subgraphs Processing Time (ms) : 12.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14749629 bytes MEM: Free's : 26 free's of 14749629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_510] 1 True 0.21
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5663861423d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1331s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.010829784728527971 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.67 Core Time (ms) : 25.42 TIDL Subgraphs Processing Time (ms) : 25.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906781 bytes MEM: Free's : 26 free's of 32906781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_341] 1 True 0.21
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b0893680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1654s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008918753625704419 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.81 Core Time (ms) : 6.27 TIDL Subgraphs Processing Time (ms) : 6.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_493] 1 True 0.44
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c64fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9485s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08192573698554081 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.87 Core Time (ms) : 29.16 TIDL Subgraphs Processing Time (ms) : 29.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32907549 bytes MEM: Free's : 26 free's of 32907549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_774] 0 - 0.08
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea80820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_627] 0 - 0.13
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f700067fcb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_247] 1 True 0.16
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df54b6a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.60s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.15257337310514446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.22 Core Time (ms) : 4.09 TIDL Subgraphs Processing Time (ms) : 4.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14768829 bytes MEM: Free's : 26 free's of 14768829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_632] 0 - 0.08
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f305863ea80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.27 Core Time (ms) : 0.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_421] 1 True 0.51
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea7e910 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8638s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0036224670822827816 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 164.95 Core Time (ms) : 153.71 TIDL Subgraphs Processing Time (ms) : 153.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395237 bytes MEM: Free's : 26 free's of 72395237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_594] 0 - 0.19
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f0da980 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_637] 0 - 0.10
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7c24f80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_760] 0 - 0.09
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30584606f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_899] 0 - 0.17
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70003b2650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_349] 1 True 0.31
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386143030 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.5104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01964539443143985 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.57 Core Time (ms) : 23.11 TIDL Subgraphs Processing Time (ms) : 23.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_864] 0 - 0.14
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187c394b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_305] 1 True 0.33
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800a7ad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2062s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0015724077532248979 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.06 Core Time (ms) : 8.60 TIDL Subgraphs Processing Time (ms) : 8.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979133 bytes MEM: Free's : 26 free's of 20979133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_625] 0 - 0.15
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b089ab10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.52 Core Time (ms) : 1.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_849] 0 - 0.16
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cd37d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.09 Core Time (ms) : 12.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_256] 1 True 0.15
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e2bdb20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1377s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1484338951537984 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.41 Core Time (ms) : 1.30 TIDL Subgraphs Processing Time (ms) : 1.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730813 bytes MEM: Free's : 26 free's of 14730813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_148] 1 True 0.24
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df6394b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2791s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.13295308756724042 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367421 bytes MEM: Free's : 26 free's of 12367421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_486] 1 True 0.26
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d018b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1625s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.24819536329925515 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.79 Core Time (ms) : 19.52 TIDL Subgraphs Processing Time (ms) : 19.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33169693 bytes MEM: Free's : 26 free's of 33169693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_913] 0 - 0.12
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7957a60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_384] 1 True 0.42
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cd3360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2489s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.023925843050008656 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 103.48 Core Time (ms) : 100.83 TIDL Subgraphs Processing Time (ms) : 100.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_468] 1 True 0.30
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f305845c8d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2157s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.009141700730692103 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 49.04 Core Time (ms) : 43.85 TIDL Subgraphs Processing Time (ms) : 43.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728797 bytes MEM: Free's : 26 free's of 40728797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_533] 1 True 0.35
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4f1c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7517s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.023730263475524333 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.69 Core Time (ms) : 45.00 TIDL Subgraphs Processing Time (ms) : 43.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67542461 bytes MEM: Free's : 26 free's of 67542461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_674] 0 - 0.12
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46309bc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.62 Core Time (ms) : 0.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_676] 0 - 0.24
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f105b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.63 Core Time (ms) : 0.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_761] 0 - 0.18
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f087c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_347] 1 True 0.20
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f700049c810 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01476242421505663 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.66 Core Time (ms) : 22.12 TIDL Subgraphs Processing Time (ms) : 22.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_110] 1 True 0.22
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1c64a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10739224991828311 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_196] 1 True 0.39
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e2c8eb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2122s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3972074260107804 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.91 Core Time (ms) : 0.83 TIDL Subgraphs Processing Time (ms) : 0.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13395133 bytes MEM: Free's : 26 free's of 13395133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_791] 0 - 0.11
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b089a810 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_843] 0 - 0.19
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cd4400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_621] 0 - 0.17
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7c28250 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_60] 1 True 0.23
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2faab030 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.29303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.29344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.29371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.29393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.29422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.29452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.29473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.29497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.29516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.29539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.29565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.29594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.29615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.29640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.29662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.29686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.29688s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.29693s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.010748381468869375 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.13 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329341 bytes MEM: Free's : 26 free's of 12329341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_459] 1 True 0.32
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00ea5c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.030381731058463552 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.67 Core Time (ms) : 14.25 TIDL Subgraphs Processing Time (ms) : 14.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728925 bytes MEM: Free's : 26 free's of 40728925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_888] 0 - 0.13
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725afd7a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_598] 0 - 0.12
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60b7c1b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_543] 1 True 0.36
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4630a160 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1578s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.047724766953704985 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 44.39 Core Time (ms) : 41.35 TIDL Subgraphs Processing Time (ms) : 41.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538749 bytes MEM: Free's : 26 free's of 67538749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_39] 1 True 0.20
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c77f10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0544146721267954 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.79 Core Time (ms) : 2.77 TIDL Subgraphs Processing Time (ms) : 2.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_227] 1 True 0.12
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df54e7e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.14164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14869s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14872s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0708144948868165 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.89 Core Time (ms) : 1.82 TIDL Subgraphs Processing Time (ms) : 1.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_209] 1 True 0.24
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b07b2a50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1958s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1960s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0007880089076556245 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.22 Core Time (ms) : 1.16 TIDL Subgraphs Processing Time (ms) : 1.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13382845 bytes MEM: Free's : 26 free's of 13382845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_521] 1 True 0.34
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5286e6e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.09567551026895728 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.95 Core Time (ms) : 44.45 TIDL Subgraphs Processing Time (ms) : 44.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67800765 bytes MEM: Free's : 26 free's of 67800765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_149] 1 True 0.22
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800ac8a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1955s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.017038001474195104 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.74 Core Time (ms) : 4.71 TIDL Subgraphs Processing Time (ms) : 4.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_763] 0 - 0.17
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004a27e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_498] 1 True 0.33
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cb81f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2121s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0008097896382289234 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.90 Core Time (ms) : 37.16 TIDL Subgraphs Processing Time (ms) : 37.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32907037 bytes MEM: Free's : 26 free's of 32907037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_668] 0 - 0.17
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee608a8fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_296] 1 True 0.24
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5917259408f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1550s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1310639006774701 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.25 Core Time (ms) : 28.77 TIDL Subgraphs Processing Time (ms) : 28.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979261 bytes MEM: Free's : 26 free's of 20979261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_183] 1 True 0.20
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f141c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1208s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4618s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4620s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1417517900813433 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.95 Core Time (ms) : 0.93 TIDL Subgraphs Processing Time (ms) : 0.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_698] 0 - 0.17
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1c70d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.88 Core Time (ms) : 6.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_657] 0 - 0.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e6ba060 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_687] 0 - 0.20
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4f32b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_450] 1 True 0.35
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a349f9660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1693s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.44592952609184033 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.92 Core Time (ms) : 37.20 TIDL Subgraphs Processing Time (ms) : 37.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41591645 bytes MEM: Free's : 26 free's of 41591645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_59] 1 True 0.31
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00eccb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10912s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002819127077892595 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.92 Core Time (ms) : 2.90 TIDL Subgraphs Processing Time (ms) : 2.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_892] 0 - 0.13
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d302860 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_286] 1 True 0.23
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004a07e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1620s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003284931436543499 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.02 Core Time (ms) : 32.59 TIDL Subgraphs Processing Time (ms) : 32.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21028029 bytes MEM: Free's : 26 free's of 21028029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_618] 0 - 0.12
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebb845b70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_188] 1 True 0.22
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c6c3b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12546s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06687418058912832 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.18 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_918] 0 - 0.30
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e2c2900 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_330] 1 True 0.48
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b03685d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0008984349986030211 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.61 Core Time (ms) : 52.19 TIDL Subgraphs Processing Time (ms) : 52.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24901821 bytes MEM: Free's : 26 free's of 24901821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_205] 1 True 0.28
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f0e75b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4327910828005997 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.68 Core Time (ms) : 14.59 TIDL Subgraphs Processing Time (ms) : 14.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13395133 bytes MEM: Free's : 26 free's of 13395133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_41] 1 True 0.25
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800ad320 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6014s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6017s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.039370777683240536 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_653] 0 - 0.19
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e6ba130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_631] 0 - 0.19
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c1880f6b50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_120] 1 True 0.28
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df63edf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.29985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.30029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.30054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.30079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.30105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.30131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.30159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.30182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.30205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.30227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.30246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.30265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.30292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.30316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.30344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.30369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.30396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.30424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.30448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.30471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.30499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.30521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.30543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.30571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.30591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.30624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.30649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.30668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.30689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.30712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.30734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.30751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.30777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.30795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.30817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.30839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.30862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.30880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.30905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.30929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.30960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.30964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.30966s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12019858773165094 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.82 Core Time (ms) : 7.80 TIDL Subgraphs Processing Time (ms) : 7.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_124] 1 True 0.29
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638614ffd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.14322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15394s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.373259621767668 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.20 Core Time (ms) : 6.17 TIDL Subgraphs Processing Time (ms) : 6.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367805 bytes MEM: Free's : 26 free's of 12367805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_52] 1 True 0.26
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725942ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08652042678971432 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.63 Core Time (ms) : 2.61 TIDL Subgraphs Processing Time (ms) : 2.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_70] 1 True 0.21
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058463b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1542s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1543s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04378715103948393 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.35 Core Time (ms) : 1.33 TIDL Subgraphs Processing Time (ms) : 1.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328885 bytes MEM: Free's : 26 free's of 12328885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_527] 1 True 0.36
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d102630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.25836383517813544 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 78.79 Core Time (ms) : 75.09 TIDL Subgraphs Processing Time (ms) : 75.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68324925 bytes MEM: Free's : 26 free's of 68324925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_585] 0 - 0.17
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a40a530 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_836] 0 - 0.10
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2facd670 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_550] 1 True 0.47
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cbb280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.17139s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08381732658319216 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.34 Core Time (ms) : 47.89 TIDL Subgraphs Processing Time (ms) : 47.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538749 bytes MEM: Free's : 26 free's of 67538749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_181] 1 True 0.30
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f0ed90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1547s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008904847221137276 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.03 Core Time (ms) : 9.00 TIDL Subgraphs Processing Time (ms) : 8.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_766] 0 - 0.13
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c6e2c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_377] 1 True 0.33
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004a3490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12690s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12693s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03448927530905561 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 68.21 Core Time (ms) : 66.28 TIDL Subgraphs Processing Time (ms) : 66.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52183485 bytes MEM: Free's : 26 free's of 52183485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_814] 0 - 0.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e99d660 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_139] 1 True 0.25
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f15c30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.020375925818904225 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.77 Core Time (ms) : 1.75 TIDL Subgraphs Processing Time (ms) : 1.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_145] 1 True 0.12
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fab2fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10023000770781196 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.05 Core Time (ms) : 2.03 TIDL Subgraphs Processing Time (ms) : 1.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_298] 1 True 0.30
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800ade20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10148s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02197197809393131 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.45 Core Time (ms) : 13.85 TIDL Subgraphs Processing Time (ms) : 13.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979645 bytes MEM: Free's : 26 free's of 20979645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_655] 0 - 0.16
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebb82fb40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_223] 1 True 0.24
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00040a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.17855322958840886 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.81 Core Time (ms) : 2.74 TIDL Subgraphs Processing Time (ms) : 2.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_855] 0 - 0.06
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30584824c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_458] 1 True 0.23
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1cb580 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6610s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06456488315060159 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.46 Core Time (ms) : 26.84 TIDL Subgraphs Processing Time (ms) : 26.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40729565 bytes MEM: Free's : 26 free's of 40729565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_873] 0 - 0.18
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f029fc7200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_118] 1 True 0.24
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5917259451b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10458s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004998127282581439 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.84 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_683] 0 - 0.21
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df63f340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.72 Core Time (ms) : 3.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_500] 1 True 0.38
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c6b210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.14667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15584s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15587s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08374982066654682 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.83 Core Time (ms) : 36.21 TIDL Subgraphs Processing Time (ms) : 36.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32907037 bytes MEM: Free's : 26 free's of 32907037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_49] 1 True 0.23
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4630f520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2033s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2036s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.027210129652326564 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.01 Core Time (ms) : 3.99 TIDL Subgraphs Processing Time (ms) : 3.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_102] 1 True 0.28
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea84af0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9051s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0017598843446490003 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.69 Core Time (ms) : 4.67 TIDL Subgraphs Processing Time (ms) : 4.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_786] 0 - 0.12
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fab89a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_782] 0 - 0.06
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528aaee80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_176] 1 True 0.22
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f11370 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4354s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04462370934020618 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.82 Core Time (ms) : 4.80 TIDL Subgraphs Processing Time (ms) : 4.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_582] 0 - 0.11
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e795f7e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_325] 1 True 0.25
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f78da2c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5165s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.28304182000970973 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.83 Core Time (ms) : 17.54 TIDL Subgraphs Processing Time (ms) : 17.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25055421 bytes MEM: Free's : 26 free's of 25055421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_917] 0 - 0.08
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d305150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_680] 0 - 0.17
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b089e9d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_561] 0 - 0.07
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5289c3f50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_626] 0 - 0.17
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a6db4a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_654] 0 - 0.32
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187b4fa10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.36 Core Time (ms) : 7.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_538] 1 True 0.57
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fab4b90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1562s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03264223261033645 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 102.61 Core Time (ms) : 99.29 TIDL Subgraphs Processing Time (ms) : 99.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67541181 bytes MEM: Free's : 26 free's of 67541181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_466] 1 True 0.41
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1cd640 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13243s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13245s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05913449687516604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 100.17 Core Time (ms) : 97.44 TIDL Subgraphs Processing Time (ms) : 97.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728413 bytes MEM: Free's : 26 free's of 40728413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_908] 0 - 0.22
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34bf0fe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_694] 0 - 0.17
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3af290 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.76 Core Time (ms) : 1.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_115] 1 True 0.24
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004a4930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2171s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2173s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01904600164239009 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.63 Core Time (ms) : 3.61 TIDL Subgraphs Processing Time (ms) : 3.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_818] 0 - 0.09
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7964770 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_495] 1 True 0.28
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df641810 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2221s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2223s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0772251235346311 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.61 Core Time (ms) : 24.35 TIDL Subgraphs Processing Time (ms) : 24.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32908189 bytes MEM: Free's : 26 free's of 32908189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_418] 1 True 0.46
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3f0e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1449s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.33171649252369123 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.10 Core Time (ms) : 33.46 TIDL Subgraphs Processing Time (ms) : 33.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72396389 bytes MEM: Free's : 26 free's of 72396389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_81] 1 True 0.35
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5917259480e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.16124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18089s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0067173310397656266 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.18 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_813] 0 - 0.07
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b374f560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_817] 0 - 0.11
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638606cce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_78] 1 True 0.24
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46312120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3806s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3809s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0001250281455596599 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.85 Core Time (ms) : 0.83 TIDL Subgraphs Processing Time (ms) : 0.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_589] 0 - 0.13
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e79621e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_634] 0 - 0.12
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b0a81ed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.56 Core Time (ms) : 0.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_699] 0 - 0.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea85ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.15 Core Time (ms) : 5.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_549] 1 True 0.39
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f0ed50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1449s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.055424555259521856 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 81.57 Core Time (ms) : 74.28 TIDL Subgraphs Processing Time (ms) : 74.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538749 bytes MEM: Free's : 26 free's of 67538749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_563] 0 - 0.17
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4155c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_881] 0 - 0.09
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3e78550 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_309] 1 True 0.28
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3b0cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0016970768566434934 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.89 Core Time (ms) : 8.44 TIDL Subgraphs Processing Time (ms) : 8.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979133 bytes MEM: Free's : 26 free's of 20979133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_879] 0 - 0.12
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386154030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_333] 1 True 0.30
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c6cb50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19449s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08030128546330884 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.12 Core Time (ms) : 13.36 TIDL Subgraphs Processing Time (ms) : 13.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825661 bytes MEM: Free's : 26 free's of 24825661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_578] 0 - 0.09
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058380ab0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_108] 1 True 0.37
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00f57b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.22189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07171855823574892 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.81 Core Time (ms) : 6.79 TIDL Subgraphs Processing Time (ms) : 6.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_382] 1 True 0.26
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cdcc10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0007075229218269486 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.13 Core Time (ms) : 41.06 TIDL Subgraphs Processing Time (ms) : 40.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_17] 1 True 0.24
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b089f9e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2478s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03395859382546246 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.65 Core Time (ms) : 11.63 TIDL Subgraphs Processing Time (ms) : 11.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332665 bytes MEM: Free's : 26 free's of 12332665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_449] 1 True 0.24
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3960a50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12482s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0016203626931551678 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.39 Core Time (ms) : 17.73 TIDL Subgraphs Processing Time (ms) : 17.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40872157 bytes MEM: Free's : 26 free's of 40872157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_297] 1 True 0.25
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004a77f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06613612620587819 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.99 Core Time (ms) : 26.49 TIDL Subgraphs Processing Time (ms) : 26.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20981309 bytes MEM: Free's : 26 free's of 20981309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_179] 1 True 0.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a510c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3820s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3823s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08191816736370694 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.25 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_424] 1 True 0.72
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea87ec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20994s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20996s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11611733498583894 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 196.72 Core Time (ms) : 177.89 TIDL Subgraphs Processing Time (ms) : 177.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395237 bytes MEM: Free's : 26 free's of 72395237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_628] 0 - 0.18
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df6470b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_177] 1 True 0.13
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058470950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8846s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8848s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1390554783402752 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.20 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_259] 1 True 0.36
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187e2cda0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8958s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0991564336221122 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.06 Core Time (ms) : 1.94 TIDL Subgraphs Processing Time (ms) : 1.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730813 bytes MEM: Free's : 26 free's of 14730813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_481] 1 True 0.28
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a45f75510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4520s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07956133173073411 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.09 Core Time (ms) : 20.97 TIDL Subgraphs Processing Time (ms) : 20.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32994205 bytes MEM: Free's : 26 free's of 32994205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_807] 0 - 0.08
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725863450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_483] 1 True 0.32
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f78da340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1699s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1701s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.19558029812030486 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.87 Core Time (ms) : 35.55 TIDL Subgraphs Processing Time (ms) : 35.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33169693 bytes MEM: Free's : 26 free's of 33169693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_752] 0 - 0.11
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30584728f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_878] 0 - 0.08
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3b4180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.66 Core Time (ms) : 1.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_597] 0 - 0.13
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172585ff90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_541] 1 True 0.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3f2ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.051080163944325366 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 77.40 Core Time (ms) : 73.96 TIDL Subgraphs Processing Time (ms) : 73.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538749 bytes MEM: Free's : 26 free's of 67538749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_540] 1 True 0.66
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cc10e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2012s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06097001848767572 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 167.13 Core Time (ms) : 162.23 TIDL Subgraphs Processing Time (ms) : 162.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67539261 bytes MEM: Free's : 26 free's of 67539261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_573] 0 - 0.13
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34bf5990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_211] 1 True 0.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b07b7150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10312385764397737 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.52 Core Time (ms) : 16.42 TIDL Subgraphs Processing Time (ms) : 16.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_292] 1 True 0.23
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1cfdd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1500s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1502s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.050432102404701314 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.53 Core Time (ms) : 15.11 TIDL Subgraphs Processing Time (ms) : 15.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20980029 bytes MEM: Free's : 26 free's of 20980029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_808] 0 - 0.23
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df55f120 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_61] 1 True 0.33
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004aa5c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.178s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.21563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.21621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.21649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.21678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.21700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.21729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.21752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.21777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.21799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.21827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.21856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.21883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.21906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.21930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.22009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.22031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.22059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.22086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.22105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.22128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.22158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.22189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.22213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.22239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.22262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.22286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.22311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.22331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.22351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.22379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.22399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22530s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22532s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07230710360140599 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328885 bytes MEM: Free's : 26 free's of 12328885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_696] 0 - 0.19
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c6ecb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_858] 0 - 0.08
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800d6360 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_244] 1 True 0.24
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9cd1b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.15093180382633187 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.72 Core Time (ms) : 5.57 TIDL Subgraphs Processing Time (ms) : 5.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14768829 bytes MEM: Free's : 26 free's of 14768829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_905] 0 - 0.16
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30583851f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_80] 1 True 0.25
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3b5240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2018s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.024431681312613203 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.76 Core Time (ms) : 0.73 TIDL Subgraphs Processing Time (ms) : 0.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_870] 0 - 0.16
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566385dab400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_519] 1 True 0.42
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4602efe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3522s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3886674201337877 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 69.75 Core Time (ms) : 64.81 TIDL Subgraphs Processing Time (ms) : 64.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68980029 bytes MEM: Free's : 26 free's of 68980029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_43] 1 True 0.39
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528ab37d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.149s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12396s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.013976566339137936 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_425] 1 True 0.39
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172594b7f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1178s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4050s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4053s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.015662439239127766 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.79 Core Time (ms) : 38.06 TIDL Subgraphs Processing Time (ms) : 37.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395621 bytes MEM: Free's : 26 free's of 72395621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_584] 0 - 0.08
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427ffd0e00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_604] 0 - 0.10
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34ef7630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_866] 0 - 0.10
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187c2b900 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_809] 0 - 0.10
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e79716a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_650] 0 - 0.13
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb02dd630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_419] 1 True 0.49
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c70a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5794s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.30516564440911 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 102.22 Core Time (ms) : 89.32 TIDL Subgraphs Processing Time (ms) : 89.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395749 bytes MEM: Free's : 26 free's of 72395749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_47] 1 True 0.24
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800bc320 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.14803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0015984500151867873 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_829] 0 - 0.10
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7ca4d00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_759] 0 - 0.13
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a57550 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_629] 0 - 0.09
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f214c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_872] 0 - 0.20
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638615a1e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.37 Core Time (ms) : 5.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_567] 0 - 0.09
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9d2c00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_380] 1 True 0.35
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08a51a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4961s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4964s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011570770358093736 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 86.11 Core Time (ms) : 84.52 TIDL Subgraphs Processing Time (ms) : 84.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52185917 bytes MEM: Free's : 26 free's of 52185917 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_675] 0 - 0.09
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00fb4d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_825] 0 - 0.15
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70003c3700 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_777] 0 - 0.15
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3ba290 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_507] 1 True 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f1a460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1664s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1666s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.025490825590782015 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.53 Core Time (ms) : 22.31 TIDL Subgraphs Processing Time (ms) : 22.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906653 bytes MEM: Free's : 26 free's of 32906653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_571] 0 - 0.09
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7b9cef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_306] 1 True 0.27
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1d4a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1391s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0723002922483742 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.26 Core Time (ms) : 15.79 TIDL Subgraphs Processing Time (ms) : 15.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979133 bytes MEM: Free's : 26 free's of 20979133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_84] 1 True 0.18
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fab9be0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0175147961538062 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.95 Core Time (ms) : 1.93 TIDL Subgraphs Processing Time (ms) : 1.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_652] 0 - 0.25
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7685030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.43 Core Time (ms) : 15.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_819] 0 - 0.09
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6e2f630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_374] 1 True 0.31
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3f55d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.024211271459981202 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 87.96 Core Time (ms) : 83.77 TIDL Subgraphs Processing Time (ms) : 83.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52182717 bytes MEM: Free's : 26 free's of 52182717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_135] 1 True 0.16
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058474d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1475s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.41659413336109596 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12368189 bytes MEM: Free's : 26 free's of 12368189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_463] 1 True 0.30
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800bdd50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.049349175571277895 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.24 Core Time (ms) : 36.84 TIDL Subgraphs Processing Time (ms) : 36.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728413 bytes MEM: Free's : 26 free's of 40728413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_42] 1 True 0.19
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c887f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6611s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08028732683499498 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_269] 1 True 0.16
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638606fb00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0033074812322641113 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.81 Core Time (ms) : 4.62 TIDL Subgraphs Processing Time (ms) : 3.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_289] 1 True 0.20
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34ce4cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3980s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3982s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003626908852094865 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.52 Core Time (ms) : 9.04 TIDL Subgraphs Processing Time (ms) : 8.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21028029 bytes MEM: Free's : 26 free's of 21028029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_301] 1 True 0.22
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004aae00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1722s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1724s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11770436104980585 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.61 Core Time (ms) : 12.15 TIDL Subgraphs Processing Time (ms) : 12.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979133 bytes MEM: Free's : 26 free's of 20979133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_868] 0 - 0.16
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6b499b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_53] 1 True 0.22
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea89d20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4634s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10424923817282998 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.15 Core Time (ms) : 6.13 TIDL Subgraphs Processing Time (ms) : 6.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_592] 0 - 0.15
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725863770 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.15 Core Time (ms) : 1.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_562] 0 - 0.13
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a462333e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_178] 1 True 0.18
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fac0360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1581s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1582s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1534674314174078 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.18 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403261 bytes MEM: Free's : 26 free's of 12403261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_666] 0 - 0.11
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f305809fc90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.23 Core Time (ms) : 11.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_114] 1 True 0.13
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df64a570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1682s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01284103607845106 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.11 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_528] 1 True 0.37
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4dfe60b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2026s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04417461192146158 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 133.55 Core Time (ms) : 129.71 TIDL Subgraphs Processing Time (ms) : 129.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67669693 bytes MEM: Free's : 26 free's of 67669693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_649] 0 - 0.07
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbde65e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_882] 0 - 0.09
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5663863169e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_545] 1 True 0.37
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a52930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4694s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0695847599333067 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 62.58 Core Time (ms) : 59.40 TIDL Subgraphs Processing Time (ms) : 59.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538749 bytes MEM: Free's : 26 free's of 67538749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_861] 0 - 0.07
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3900b50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_602] 0 - 0.08
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187bb3d40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_671] 0 - 0.11
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725950230 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_420] 1 True 0.32
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4ff680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5910s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5912s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.29839328625029815 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 80.65 Core Time (ms) : 77.39 TIDL Subgraphs Processing Time (ms) : 77.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395749 bytes MEM: Free's : 26 free's of 72395749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_859] 0 - 0.06
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7ca7ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_363] 1 True 0.49
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6b4ac20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6043s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6045s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.25238400741838823 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 156.23 Core Time (ms) : 153.86 TIDL Subgraphs Processing Time (ms) : 153.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52771005 bytes MEM: Free's : 26 free's of 52771005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_780] 0 - 0.10
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08a89f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_239] 1 True 0.26
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30580cfc80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4863359472351412 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.20 Core Time (ms) : 12.07 TIDL Subgraphs Processing Time (ms) : 12.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14807229 bytes MEM: Free's : 26 free's of 14807229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_378] 1 True 0.49
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c741c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16089s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02738003150185629 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.91 Core Time (ms) : 43.20 TIDL Subgraphs Processing Time (ms) : 43.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52183485 bytes MEM: Free's : 26 free's of 52183485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_270] 1 True 0.27
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70003c3430 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.13443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14210s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05211694045940586 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.58 Core Time (ms) : 2.43 TIDL Subgraphs Processing Time (ms) : 2.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_184] 1 True 0.23
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea8fc00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07536276629018973 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.71 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_343] 1 True 0.31
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3f5dc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8889s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.015076226283980141 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.16 Core Time (ms) : 10.61 TIDL Subgraphs Processing Time (ms) : 10.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_5] 1 True 0.22
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c8c4f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.055501687104905974 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.92 Core Time (ms) : 0.90 TIDL Subgraphs Processing Time (ms) : 0.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332665 bytes MEM: Free's : 26 free's of 12332665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_441] 1 True 0.30
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebb82faf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5590s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11188922757517299 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.27 Core Time (ms) : 20.09 TIDL Subgraphs Processing Time (ms) : 20.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40872157 bytes MEM: Free's : 26 free's of 40872157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_661] 0 - 0.24
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df2ff190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_222] 1 True 0.29
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f0efcd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.047127448149654985 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.66 Core Time (ms) : 0.60 TIDL Subgraphs Processing Time (ms) : 0.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370941 bytes MEM: Free's : 26 free's of 13370941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_869] 0 - 0.24
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b39dc9e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.33 Core Time (ms) : 0.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_897] 0 - 0.18
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187e333e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_56] 1 True 0.22
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528ab7ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1773s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1776s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.024902511262943478 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.80 Core Time (ms) : 3.78 TIDL Subgraphs Processing Time (ms) : 3.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329341 bytes MEM: Free's : 26 free's of 12329341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_192] 1 True 0.32
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9d4680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1641s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1643s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4091809511713379 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.88 Core Time (ms) : 0.81 TIDL Subgraphs Processing Time (ms) : 0.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13419709 bytes MEM: Free's : 26 free's of 13419709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_310] 1 True 0.27
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08a59a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.25006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.25026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.25054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.25082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25184s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.016701660910983053 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.86 Core Time (ms) : 5.34 TIDL Subgraphs Processing Time (ms) : 5.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979261 bytes MEM: Free's : 26 free's of 20979261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_580] 0 - 0.18
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725864eb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_253] 1 True 0.22
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb00190a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1676s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11134571260260415 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.06 Core Time (ms) : 7.91 TIDL Subgraphs Processing Time (ms) : 7.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14731453 bytes MEM: Free's : 26 free's of 14731453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_852] 0 - 0.12
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46337d20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_456] 1 True 0.42
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f1f130 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6115s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6118s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03389505957998106 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.44 Core Time (ms) : 37.53 TIDL Subgraphs Processing Time (ms) : 37.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40730333 bytes MEM: Free's : 26 free's of 40730333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_208] 1 True 0.26
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427ffda4a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6175s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4114587326071944 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.37 Core Time (ms) : 2.29 TIDL Subgraphs Processing Time (ms) : 2.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13419709 bytes MEM: Free's : 26 free's of 13419709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_910] 0 - 0.07
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7ba2fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_408] 1 True 0.67
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f305810fc30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12150s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12153s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05111330857154175 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 95.50 Core Time (ms) : 90.43 TIDL Subgraphs Processing Time (ms) : 90.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70579597 bytes MEM: Free's : 26 free's of 70579597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_89] 1 True 0.31
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725950ab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6893s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6896s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008590316779869215 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_376] 1 True 0.32
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4631b6d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17162s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17164s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08096148288542485 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.27 Core Time (ms) : 28.27 TIDL Subgraphs Processing Time (ms) : 28.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181949 bytes MEM: Free's : 26 free's of 52181949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_847] 0 - 0.14
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528ad77e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_127] 1 True 0.21
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df64f980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9242s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9243s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3719768454814426 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.99 Core Time (ms) : 4.97 TIDL Subgraphs Processing Time (ms) : 4.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367805 bytes MEM: Free's : 26 free's of 12367805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_87] 1 True 0.22
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cc5ec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12768s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0011647160876431502 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.11 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_144] 1 True 0.27
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a504010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0809424767900414 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.65 Core Time (ms) : 10.63 TIDL Subgraphs Processing Time (ms) : 10.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_773] 0 - 0.11
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3bf5b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_267] 1 True 0.29
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70003c5610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1987s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1989s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.018268317654691377 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.09 Core Time (ms) : 2.97 TIDL Subgraphs Processing Time (ms) : 2.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_670] 0 - 0.27
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f774a740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.61 Core Time (ms) : 0.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_525] 1 True 0.65
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbc06660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.35107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.35866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.35880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.35898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.35910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.35930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.35947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.35958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.35969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.35981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.35994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.36013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.36027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.36040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.36060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.36071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.36083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.36098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.36109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.36132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.36149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.36159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.36172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.36186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.36199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.36212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.36227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.36240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.36251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.36267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.36279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.36293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.36308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.36320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.36331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.36345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.36356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.36372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.36386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.36400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.36415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.36432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.36433s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.36435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.2192722258261425 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 109.33 Core Time (ms) : 104.72 TIDL Subgraphs Processing Time (ms) : 104.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68324925 bytes MEM: Free's : 26 free's of 68324925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_794] 0 - 0.13
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1e0630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_751] 0 - 0.14
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb010a730 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_837] 0 - 0.12
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d416010 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_321] 1 True 0.35
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f718a00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1741s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008516222658737171 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.21 Core Time (ms) : 14.90 TIDL Subgraphs Processing Time (ms) : 14.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24901821 bytes MEM: Free's : 26 free's of 24901821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_790] 0 - 0.06
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386163950 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_779] 0 - 0.20
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3c0120 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_447] 1 True 0.41
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5286e6f20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10370882272315758 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 90.41 Core Time (ms) : 84.73 TIDL Subgraphs Processing Time (ms) : 84.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41016029 bytes MEM: Free's : 26 free's of 41016029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_304] 1 True 0.25
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386161990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1360s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0007501921322903243 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.58 Core Time (ms) : 18.12 TIDL Subgraphs Processing Time (ms) : 18.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979133 bytes MEM: Free's : 26 free's of 20979133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_48] 1 True 0.23
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1de190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1742s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0002482393032117159 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.40 Core Time (ms) : 3.38 TIDL Subgraphs Processing Time (ms) : 3.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_26] 1 True 0.23
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb01072e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.164s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06581989183467978 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332537 bytes MEM: Free's : 26 free's of 12332537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_140] 1 True 0.28
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df6521d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1759s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03708785440412586 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_798] 0 - 0.15
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cc9ac0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_462] 1 True 0.38
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800c6990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4159s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06882306007515097 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.21 Core Time (ms) : 45.64 TIDL Subgraphs Processing Time (ms) : 45.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728413 bytes MEM: Free's : 26 free's of 40728413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_603] 0 - 0.09
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a19b2a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_880] 0 - 0.08
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725570040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.40 Core Time (ms) : 0.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_522] 1 True 0.34
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f793a2a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013814178357586036 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 61.01 Core Time (ms) : 57.84 TIDL Subgraphs Processing Time (ms) : 57.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67669693 bytes MEM: Free's : 26 free's of 67669693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_132] 1 True 0.26
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46320510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.19336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.19378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.19397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.19423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.19451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.19474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.19499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.19526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.19545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.19565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.19589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.19608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.19637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.19662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.19680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20067s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05355051923209002 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.86 Core Time (ms) : 3.83 TIDL Subgraphs Processing Time (ms) : 3.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367421 bytes MEM: Free's : 26 free's of 12367421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_31] 1 True 0.28
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a5a8b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2175s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3448710764126865 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_365] 1 True 0.28
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4dfe6020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1426s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1428s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.25183692232626564 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 68.75 Core Time (ms) : 67.03 TIDL Subgraphs Processing Time (ms) : 66.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52771005 bytes MEM: Free's : 26 free's of 52771005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_45] 1 True 0.32
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f20350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3303352665002745 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.32 Core Time (ms) : 4.29 TIDL Subgraphs Processing Time (ms) : 4.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329341 bytes MEM: Free's : 26 free's of 12329341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_467] 1 True 0.30
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cc7be0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8247s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006227381992296323 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.82 Core Time (ms) : 34.40 TIDL Subgraphs Processing Time (ms) : 34.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728413 bytes MEM: Free's : 26 free's of 40728413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_665] 0 - 0.19
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a136e90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.59 Core Time (ms) : 2.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_553] 0 - 0.24
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee608d8ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_299] 1 True 0.30
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725951c60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1764s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07785055022743395 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.23 Core Time (ms) : 11.60 TIDL Subgraphs Processing Time (ms) : 11.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979645 bytes MEM: Free's : 26 free's of 20979645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_499] 1 True 0.21
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1e01c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1812s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1814s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.054633776015189546 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.44 Core Time (ms) : 14.14 TIDL Subgraphs Processing Time (ms) : 14.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32907037 bytes MEM: Free's : 26 free's of 32907037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_830] 0 - 0.14
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386181d30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_526] 1 True 0.35
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70000f7f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1463s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11846700119695848 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.64 Core Time (ms) : 40.13 TIDL Subgraphs Processing Time (ms) : 40.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67931709 bytes MEM: Free's : 26 free's of 67931709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_524] 1 True 0.35
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cafd4f9b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.17311398918441734 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.45 Core Time (ms) : 35.08 TIDL Subgraphs Processing Time (ms) : 35.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67931709 bytes MEM: Free's : 26 free's of 67931709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_691] 0 - 0.09
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fac1420 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.73 Core Time (ms) : 0.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_630] 0 - 0.14
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df8375b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_185] 1 True 0.20
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528ac0d50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08621661797219429 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.22 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_617] 0 - 0.11
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea95560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_787] 0 - 0.13
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fac6b00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_893] 0 - 0.19
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a41c300 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_554] 0 - 0.09
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a45f75510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_111] 1 True 0.23
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f1f3a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.017955867280974914 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.76 Core Time (ms) : 2.74 TIDL Subgraphs Processing Time (ms) : 2.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334293 bytes MEM: Free's : 26 free's of 12334293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_261] 1 True 0.21
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b07c47a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16495s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004600613613106289 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.56 Core Time (ms) : 1.41 TIDL Subgraphs Processing Time (ms) : 1.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_426] 1 True 0.51
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800c89e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.015347385841078715 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 85.62 Core Time (ms) : 78.26 TIDL Subgraphs Processing Time (ms) : 78.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395237 bytes MEM: Free's : 26 free's of 72395237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_574] 0 - 0.12
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7973b10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_328] 1 True 0.25
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee608d8fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.009591397354470309 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.55 Core Time (ms) : 15.33 TIDL Subgraphs Processing Time (ms) : 15.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24901821 bytes MEM: Free's : 26 free's of 24901821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_303] 1 True 0.32
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3bf1f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.012655848579984965 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.14 Core Time (ms) : 13.45 TIDL Subgraphs Processing Time (ms) : 13.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979133 bytes MEM: Free's : 26 free's of 20979133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_824] 0 - 0.11
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34d0ad00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_143] 1 True 0.16
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1e3fa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1761s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1764s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006457113552779593 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.19 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_491] 1 True 0.30
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d3ff3d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01736844288092087 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.71 Core Time (ms) : 22.58 TIDL Subgraphs Processing Time (ms) : 22.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32907037 bytes MEM: Free's : 26 free's of 32907037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_415] 1 True 0.32
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058479380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.32683012036778275 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.59 Core Time (ms) : 40.43 TIDL Subgraphs Processing Time (ms) : 40.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395749 bytes MEM: Free's : 26 free's of 72395749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_287] 1 True 0.42
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df6aad80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15124s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15127s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.2195708621499741 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.59 Core Time (ms) : 16.38 TIDL Subgraphs Processing Time (ms) : 16.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21077181 bytes MEM: Free's : 26 free's of 21077181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_27] 1 True 0.42
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cca120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17122s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.020942312914910447 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.78 Core Time (ms) : 11.76 TIDL Subgraphs Processing Time (ms) : 11.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332537 bytes MEM: Free's : 26 free's of 12332537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_290] 1 True 0.41
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea901a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.21076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.21113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.21150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.21172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.21203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.21228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.21248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.21271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.21292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.21317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.21340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.21425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.21450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.21478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.21499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.21519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.21542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.21561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.21580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.21604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.21628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.21654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.21680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.21702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.21721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.21747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.22002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.22025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.22047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22134s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.09752760025800337 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.90 Core Time (ms) : 41.47 TIDL Subgraphs Processing Time (ms) : 41.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21028029 bytes MEM: Free's : 26 free's of 21028029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_834] 0 - 0.10
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4633d830 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_648] 0 - 0.15
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c188105ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_887] 0 - 0.11
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fc7e260 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.38 Core Time (ms) : 1.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_647] 0 - 0.12
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbdeb8d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.27 Core Time (ms) : 0.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_860] 0 - 0.09
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725971d00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_555] 0 - 0.08
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a349102c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_874] 0 - 0.12
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a5dfb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_796] 0 - 0.11
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528ac20f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_230] 1 True 0.27
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a41c750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1519s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0650632080695256 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.87 Core Time (ms) : 0.80 TIDL Subgraphs Processing Time (ms) : 0.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_407] 1 True 0.26
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70000f7f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1859s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.15859000248574617 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 65.90 Core Time (ms) : 60.57 TIDL Subgraphs Processing Time (ms) : 60.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70877965 bytes MEM: Free's : 26 free's of 70877965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_216] 1 True 0.20
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172586c160 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12646s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.031521748367149154 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.71 Core Time (ms) : 0.64 TIDL Subgraphs Processing Time (ms) : 0.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370941 bytes MEM: Free's : 26 free's of 13370941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_795] 0 - 0.15
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1e7140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_909] 0 - 0.17
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9db520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_575] 0 - 0.13
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34c051b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_487] 1 True 0.37
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b04d6990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.16178896768138418 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.37 Core Time (ms) : 58.01 TIDL Subgraphs Processing Time (ms) : 57.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33169693 bytes MEM: Free's : 26 free's of 33169693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_651] 0 - 0.18
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187c393f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.78 Core Time (ms) : 0.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_801] 0 - 0.11
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5289de0c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_281] 1 True 0.22
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a5e6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5344s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10928563347453307 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.54 Core Time (ms) : 14.05 TIDL Subgraphs Processing Time (ms) : 13.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21028029 bytes MEM: Free's : 26 free's of 21028029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_641] 0 - 0.14
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60e5f0a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.33 Core Time (ms) : 0.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_136] 1 True 0.26
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c96ce0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.5169s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7095s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7097s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10614511421876892 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.60 Core Time (ms) : 6.56 TIDL Subgraphs Processing Time (ms) : 6.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_600] 0 - 0.15
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d316ce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_886] 0 - 0.11
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34c07d20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_133] 1 True 0.31
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3c3c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0400431398751908 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.59 Core Time (ms) : 2.57 TIDL Subgraphs Processing Time (ms) : 2.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_125] 1 True 0.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f305847d250 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05409662474221916 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.68 Core Time (ms) : 1.66 TIDL Subgraphs Processing Time (ms) : 1.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367805 bytes MEM: Free's : 26 free's of 12367805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_863] 0 - 0.12
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5287d0960 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_389] 1 True 0.36
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fac54a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13155s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.09205425465958325 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.49 Core Time (ms) : 39.46 TIDL Subgraphs Processing Time (ms) : 39.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_765] 0 - 0.09
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172595a520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.01 Core Time (ms) : 0.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_891] 0 - 0.10
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60b920c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.30 Core Time (ms) : 0.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_393] 1 True 0.48
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f23970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4837541466733378 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 82.36 Core Time (ms) : 78.94 TIDL Subgraphs Processing Time (ms) : 78.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72369805 bytes MEM: Free's : 26 free's of 72369805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_591] 0 - 0.09
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a41ef50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_193] 1 True 0.23
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70003d59a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4336710432349522 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.84 Core Time (ms) : 8.77 TIDL Subgraphs Processing Time (ms) : 8.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13395133 bytes MEM: Free's : 26 free's of 13395133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_552] 0 - 0.07
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a3490fcd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_896] 0 - 0.26
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df56ae50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_175] 1 True 0.15
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172595c880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11895014959131224 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.24 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_688] 0 - 0.32
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3ccc0a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.79 Core Time (ms) : 0.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_329] 1 True 0.25
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e76bdcf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6986s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6988s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007282895691686943 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.36 Core Time (ms) : 11.15 TIDL Subgraphs Processing Time (ms) : 11.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24901821 bytes MEM: Free's : 26 free's of 24901821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_248] 1 True 0.19
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5289d8170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15992s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4401443424050953 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.75 Core Time (ms) : 6.61 TIDL Subgraphs Processing Time (ms) : 6.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14788029 bytes MEM: Free's : 26 free's of 14788029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_903] 0 - 0.26
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbb21160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_565] 0 - 0.16
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60b96240 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_422] 1 True 0.59
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cf2570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1358s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.031620719940667494 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 63.19 Core Time (ms) : 59.70 TIDL Subgraphs Processing Time (ms) : 59.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395237 bytes MEM: Free's : 26 free's of 72395237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_505] 1 True 0.30
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c96a70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1848s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1850s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10111070547807073 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.69 Core Time (ms) : 27.58 TIDL Subgraphs Processing Time (ms) : 27.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906653 bytes MEM: Free's : 26 free's of 32906653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_150] 1 True 0.21
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f305847f370 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.15207072638529834 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.84 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_606] 0 - 0.17
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08b4290 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0.4490417303632752 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.25 Core Time (ms) : 0.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_797] 0 - 0.16
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172595cd40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_564] 0 - 0.07
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f101f40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_174] 1 True 0.18
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3c7ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8769s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8771s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.040708576684679004 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_180] 1 True 0.28
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004bd9d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8923s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8928s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.45731776670434654 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.73 Core Time (ms) : 3.72 TIDL Subgraphs Processing Time (ms) : 3.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12404029 bytes MEM: Free's : 26 free's of 12404029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_372] 1 True 0.30
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528ac4660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.69s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1290s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.026009744359747827 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.07 Core Time (ms) : 36.55 TIDL Subgraphs Processing Time (ms) : 36.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52183485 bytes MEM: Free's : 26 free's of 52183485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_331] 1 True 0.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a463231d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1589s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.09140401774381263 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.25 Core Time (ms) : 6.46 TIDL Subgraphs Processing Time (ms) : 6.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825661 bytes MEM: Free's : 26 free's of 24825661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_22] 1 True 0.29
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c7e680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15570s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03122605586602068 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.76 Core Time (ms) : 4.74 TIDL Subgraphs Processing Time (ms) : 4.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332665 bytes MEM: Free's : 26 free's of 12332665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_103] 1 True 0.18
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1ea740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.46173564762810293 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.81 Core Time (ms) : 2.79 TIDL Subgraphs Processing Time (ms) : 2.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334293 bytes MEM: Free's : 26 free's of 12334293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_588] 0 - 0.22
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386080710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_116] 1 True 0.27
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df656380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.010108600484924353 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.70 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_542] 1 True 0.34
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a62920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08835056682662111 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 61.52 Core Time (ms) : 58.08 TIDL Subgraphs Processing Time (ms) : 58.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538749 bytes MEM: Free's : 26 free's of 67538749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_457] 1 True 0.25
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fac96e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.02182813744065483 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.08 Core Time (ms) : 14.39 TIDL Subgraphs Processing Time (ms) : 14.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40734301 bytes MEM: Free's : 26 free's of 40734301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_484] 1 True 0.24
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e6ef340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07464876346392435 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.37 Core Time (ms) : 30.19 TIDL Subgraphs Processing Time (ms) : 30.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32994205 bytes MEM: Free's : 26 free's of 32994205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_202] 1 True 0.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b07cfc70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.25000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.25026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25121s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.2062182283517912 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.43 Core Time (ms) : 6.34 TIDL Subgraphs Processing Time (ms) : 6.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13382845 bytes MEM: Free's : 26 free's of 13382845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_430] 1 True 0.32
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a50c780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16434s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.027641828405071126 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 56.75 Core Time (ms) : 53.81 TIDL Subgraphs Processing Time (ms) : 53.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395237 bytes MEM: Free's : 26 free's of 72395237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_295] 1 True 0.30
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172595a1d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1358s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04710947571266918 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.99 Core Time (ms) : 28.54 TIDL Subgraphs Processing Time (ms) : 28.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20980029 bytes MEM: Free's : 26 free's of 20980029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_189] 1 True 0.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30584836e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.67s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007256977055870054 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.09 Core Time (ms) : 14.06 TIDL Subgraphs Processing Time (ms) : 14.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_443] 1 True 0.28
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b39009a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4914s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1444569689422243 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.40 Core Time (ms) : 34.81 TIDL Subgraphs Processing Time (ms) : 34.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 41016029 bytes MEM: Free's : 26 free's of 41016029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_307] 1 True 0.18
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3c4b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0034859611353837447 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.26 Core Time (ms) : 5.73 TIDL Subgraphs Processing Time (ms) : 5.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979133 bytes MEM: Free's : 26 free's of 20979133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_509] 1 True 0.21
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f28e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.004603759329480489 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.85 Core Time (ms) : 11.50 TIDL Subgraphs Processing Time (ms) : 11.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906653 bytes MEM: Free's : 26 free's of 32906653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_113] 1 True 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f25660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18977s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18980s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06792432984336642 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.59 Core Time (ms) : 6.57 TIDL Subgraphs Processing Time (ms) : 6.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_445] 1 True 0.46
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fcef270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.037215033608600644 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 96.11 Core Time (ms) : 93.89 TIDL Subgraphs Processing Time (ms) : 93.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40872157 bytes MEM: Free's : 26 free's of 40872157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_531] 1 True 0.40
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638616b5b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.2101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0063929767080693495 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 71.91 Core Time (ms) : 68.68 TIDL Subgraphs Processing Time (ms) : 68.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67539261 bytes MEM: Free's : 26 free's of 67539261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_229] 1 True 0.20
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4623bab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12001993664549856 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.68 Core Time (ms) : 0.63 TIDL Subgraphs Processing Time (ms) : 0.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_620] 0 - 0.11
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c8a130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_803] 0 - 0.18
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5289dff20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_25] 1 True 0.20
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea991d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4938s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6341s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.041310662592217884 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332537 bytes MEM: Free's : 26 free's of 12332537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_823] 0 - 0.10
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fae6f40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_771] 0 - 0.21
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df65b3c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_845] 0 - 0.10
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3e4930 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_579] 0 - 0.21
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058399d50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_212] 1 True 0.22
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbb25ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5060s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05422720460894098 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.45 Core Time (ms) : 4.36 TIDL Subgraphs Processing Time (ms) : 4.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13371197 bytes MEM: Free's : 26 free's of 13371197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_635] 0 - 0.09
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f710ebc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_375] 1 True 0.29
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a65060 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1356s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008093634019641529 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.51 Core Time (ms) : 51.82 TIDL Subgraphs Processing Time (ms) : 51.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52182717 bytes MEM: Free's : 26 free's of 52182717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_619] 0 - 0.22
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08d5d40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_72] 1 True 0.14
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3ccf180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06843212803707006 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.13 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_535] 1 True 0.44
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c80920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1325s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1326s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.09320940157681773 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.79 Core Time (ms) : 63.43 TIDL Subgraphs Processing Time (ms) : 63.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67539261 bytes MEM: Free's : 26 free's of 67539261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_569] 0 - 0.09
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9e3180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_18] 1 True 0.26
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34cf4c00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4930s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 4.732621276026475e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.63 Core Time (ms) : 2.60 TIDL Subgraphs Processing Time (ms) : 2.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12333305 bytes MEM: Free's : 26 free's of 12333305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_416] 1 True 0.69
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f2bfe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.7134s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9047s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9050s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3079377704576487 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 84.49 Core Time (ms) : 80.28 TIDL Subgraphs Processing Time (ms) : 80.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72396389 bytes MEM: Free's : 26 free's of 72396389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_832] 0 - 0.09
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f20b720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_568] 0 - 0.12
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5286e6f00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_51] 1 True 0.20
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f27020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8040s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8043s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01780751292370791 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.19 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_660] 0 - 0.17
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea99810 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0.07628180036523637 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.97 Core Time (ms) : 0.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_67] 1 True 0.21
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2facb380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.125s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5751s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5755s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001121616369192251 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.82 Core Time (ms) : 0.79 TIDL Subgraphs Processing Time (ms) : 0.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_452] 1 True 0.21
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d409060 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.033166320998565056 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.28 Core Time (ms) : 18.69 TIDL Subgraphs Processing Time (ms) : 18.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728925 bytes MEM: Free's : 26 free's of 40728925 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_911] 0 - 0.12
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7bb2300 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.76 Core Time (ms) : 3.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_689] 0 - 0.15
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df658540 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.55 Core Time (ms) : 0.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_266] 1 True 0.22
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3be55f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13426s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.032601170224573164 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.82 Core Time (ms) : 4.69 TIDL Subgraphs Processing Time (ms) : 4.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_697] 0 - 0.13
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058481bc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.56 Core Time (ms) : 0.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_640] 0 - 0.10
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb02fb510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_469] 1 True 0.21
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1ef570 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.5138s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6686s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0024094653447264544 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.81 Core Time (ms) : 20.11 TIDL Subgraphs Processing Time (ms) : 20.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728413 bytes MEM: Free's : 26 free's of 40728413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_254] 1 True 0.27
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbb27790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.145s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2133s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2135s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08666114943391286 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.73 Core Time (ms) : 8.54 TIDL Subgraphs Processing Time (ms) : 8.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730813 bytes MEM: Free's : 26 free's of 14730813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_875] 0 - 0.21
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b050ea10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_783] 0 - 0.07
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386170b30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_348] 1 True 0.27
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7c9cdb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.021142291382930983 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.61 Core Time (ms) : 12.15 TIDL Subgraphs Processing Time (ms) : 12.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_146] 1 True 0.29
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb011a770 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2227s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12135738737632194 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.67 Core Time (ms) : 15.65 TIDL Subgraphs Processing Time (ms) : 15.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_599] 0 - 0.13
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a427dc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_30] 1 True 0.22
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800cfd50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.22292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.22325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.22328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.22331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07993446032201638 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.63 Core Time (ms) : 15.60 TIDL Subgraphs Processing Time (ms) : 15.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332537 bytes MEM: Free's : 26 free's of 12332537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_373] 1 True 0.38
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a669f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9021s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9024s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005726063131841583 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 69.73 Core Time (ms) : 67.44 TIDL Subgraphs Processing Time (ms) : 67.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181949 bytes MEM: Free's : 26 free's of 52181949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_308] 1 True 0.23
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea99130 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031531841911204225 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.81 Core Time (ms) : 10.40 TIDL Subgraphs Processing Time (ms) : 10.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979261 bytes MEM: Free's : 26 free's of 20979261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_865] 0 - 0.23
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058189d90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_559] 0 - 0.20
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5917255b94d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_595] 0 - 0.20
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df56f740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_811] 0 - 0.23
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34c17560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_685] 0 - 0.19
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3d0280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_231] 1 True 0.22
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187bbf8d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4870508669993842 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.76 Core Time (ms) : 5.61 TIDL Subgraphs Processing Time (ms) : 5.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14884029 bytes MEM: Free's : 26 free's of 14884029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_906] 0 - 0.19
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d320820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_770] 0 - 0.14
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386171d80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_758] 0 - 0.11
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fad0360 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_131] 1 True 0.19
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cd4280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01309023016300324 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.12 Core Time (ms) : 7.09 TIDL Subgraphs Processing Time (ms) : 7.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_264] 1 True 0.16
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1069d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0037110866495042192 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.09 Core Time (ms) : 4.95 TIDL Subgraphs Processing Time (ms) : 4.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_199] 1 True 0.18
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9ec410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11898s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4310163234866372 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.47 Core Time (ms) : 2.38 TIDL Subgraphs Processing Time (ms) : 2.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13395133 bytes MEM: Free's : 26 free's of 13395133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_260] 1 True 0.16
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b07ce2b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011497254974672801 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.27 Core Time (ms) : 3.62 TIDL Subgraphs Processing Time (ms) : 3.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730813 bytes MEM: Free's : 26 free's of 14730813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_885] 0 - 0.08
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a464eb3c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_816] 0 - 0.08
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60b9cbf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_23] 1 True 0.17
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbc14560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.71s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00041137348239614856 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.12 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332665 bytes MEM: Free's : 26 free's of 12332665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_129] 1 True 0.17
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386171b90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1643s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1645s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3890638300013047 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.30 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367805 bytes MEM: Free's : 26 free's of 12367805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_29] 1 True 0.17
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df65b3b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1533s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01050616699384848 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332537 bytes MEM: Free's : 26 free's of 12332537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_667] 0 - 0.19
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5917255fb4e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.75 Core Time (ms) : 0.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_587] 0 - 0.09
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e2e8040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_417] 1 True 0.29
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea9bd70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3376577465989746 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.40 Core Time (ms) : 41.57 TIDL Subgraphs Processing Time (ms) : 41.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395749 bytes MEM: Free's : 26 free's of 72395749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_334] 1 True 0.17
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058482e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.046125561465450424 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.69 Core Time (ms) : 5.17 TIDL Subgraphs Processing Time (ms) : 5.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825661 bytes MEM: Free's : 26 free's of 24825661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_147] 1 True 0.21
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d40e0d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04175140370527336 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.12 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_503] 1 True 0.41
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7ca0aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008410399316956788 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 78.99 Core Time (ms) : 77.84 TIDL Subgraphs Processing Time (ms) : 77.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906653 bytes MEM: Free's : 26 free's of 32906653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_853] 0 - 0.08
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a4634b760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_489] 1 True 0.28
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187b87950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1384s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.014162713799953718 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.26 Core Time (ms) : 37.08 TIDL Subgraphs Processing Time (ms) : 37.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32994205 bytes MEM: Free's : 26 free's of 32994205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_38] 1 True 0.27
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb011adc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1857s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1859s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4007706760922674 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.78 Core Time (ms) : 7.76 TIDL Subgraphs Processing Time (ms) : 7.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_401] 1 True 0.59
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7ee94ff0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.72s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.14335756778289027 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 241.06 Core Time (ms) : 235.90 TIDL Subgraphs Processing Time (ms) : 235.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70579597 bytes MEM: Free's : 26 free's of 70579597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_764] 0 - 0.09
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cd6fe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_826] 0 - 0.09
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60ca1200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_590] 0 - 0.16
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70003d9e00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_213] 1 True 0.26
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9e55c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1797s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1799s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07124787812046779 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.41 Core Time (ms) : 6.33 TIDL Subgraphs Processing Time (ms) : 6.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13371837 bytes MEM: Free's : 26 free's of 13371837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_300] 1 True 0.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386172080 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1456s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.043047551208934276 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.11 Core Time (ms) : 18.66 TIDL Subgraphs Processing Time (ms) : 18.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20979261 bytes MEM: Free's : 26 free's of 20979261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_762] 0 - 0.13
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528acd7f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_812] 0 - 0.12
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3bf2900 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_916] 0 - 0.20
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60b99ce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_497] 1 True 0.28
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a68fc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10156718298091515 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.91 Core Time (ms) : 24.64 TIDL Subgraphs Processing Time (ms) : 24.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32907037 bytes MEM: Free's : 26 free's of 32907037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_835] 0 - 0.12
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df67a2d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_339] 1 True 0.29
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f30584852a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19923s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07222559296720343 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.24 Core Time (ms) : 25.71 TIDL Subgraphs Processing Time (ms) : 25.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24826045 bytes MEM: Free's : 26 free's of 24826045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_883] 0 - 0.18
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725b1cdb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_672] 0 - 0.14
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f2e8a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_332] 1 True 0.26
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d40d0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1458s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1460s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.074661942931649 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 60.11 Core Time (ms) : 59.58 TIDL Subgraphs Processing Time (ms) : 59.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825661 bytes MEM: Free's : 26 free's of 24825661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_534] 1 True 0.32
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800d58f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01583614864399444 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.04 Core Time (ms) : 55.47 TIDL Subgraphs Processing Time (ms) : 55.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67540413 bytes MEM: Free's : 26 free's of 67540413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_684] 0 - 0.21
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004c3690 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.68 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_141] 1 True 0.21
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528acd3f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10178s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10181s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03414441240014854 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367293 bytes MEM: Free's : 26 free's of 12367293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_643] 0 - 0.10
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b0a9f9d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_605] 0 - 0.22
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5c1a34906400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_548] 1 True 0.35
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cd5560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.06272392942434687 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.78 Core Time (ms) : 43.73 TIDL Subgraphs Processing Time (ms) : 43.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67538749 bytes MEM: Free's : 26 free's of 67538749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_379] 1 True 0.30
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df65dd70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1543s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1545s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.060175465305170914 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.61 Core Time (ms) : 35.69 TIDL Subgraphs Processing Time (ms) : 35.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181949 bytes MEM: Free's : 26 free's of 52181949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_844] 0 - 0.13
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f4a040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_117] 1 True 0.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69ea9e500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10415s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0016207173829210528 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.64 Core Time (ms) : 10.62 TIDL Subgraphs Processing Time (ms) : 10.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334293 bytes MEM: Free's : 26 free's of 12334293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_781] 0 - 0.09
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c88440 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_50] 1 True 0.24
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f2ee20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.147s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1580s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1582s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.021283776449524994 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.19 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_265] 1 True 0.22
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725878bd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5924s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5928s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0024594419266302237 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.04 Core Time (ms) : 3.90 TIDL Subgraphs Processing Time (ms) : 3.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_838] 0 - 0.07
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08d99a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_529] 1 True 0.32
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f6ed1e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1764765287468307 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.04 Core Time (ms) : 59.55 TIDL Subgraphs Processing Time (ms) : 59.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67931709 bytes MEM: Free's : 26 free's of 67931709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_32] 1 True 0.22
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a6ba90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1965s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1967s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.327836494948769 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.78 Core Time (ms) : 6.76 TIDL Subgraphs Processing Time (ms) : 6.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329341 bytes MEM: Free's : 26 free's of 12329341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_784] 0 - 0.17
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f30740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_902] 0 - 0.16
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7bb9080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.49 Core Time (ms) : 2.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_494] 1 True 0.32
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c86b50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.18022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18372s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008201665513983504 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.67 Core Time (ms) : 21.17 TIDL Subgraphs Processing Time (ms) : 21.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32908189 bytes MEM: Free's : 26 free's of 32908189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_173] 1 True 0.26
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08c1590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1395s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.061302347323607675 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.71 Core Time (ms) : 6.69 TIDL Subgraphs Processing Time (ms) : 6.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_46] 1 True 0.25
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3d4170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1453s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.01178607344243573 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.04 Core Time (ms) : 10.01 TIDL Subgraphs Processing Time (ms) : 9.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_383] 1 True 0.32
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058487e00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1842s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.007569424428005112 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 49.24 Core Time (ms) : 47.40 TIDL Subgraphs Processing Time (ms) : 47.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_607] 0 - 0.12
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d528758ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_890] 0 - 0.11
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d328f70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_130] 1 True 0.20
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46332ad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.34993748078135084 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367805 bytes MEM: Free's : 26 free's of 12367805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_361] 1 True 0.33
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70000f86d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1826s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1828s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.3045723960418244 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.60 Core Time (ms) : 23.86 TIDL Subgraphs Processing Time (ms) : 23.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52771005 bytes MEM: Free's : 26 free's of 52771005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_914] 0 - 0.13
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a431330 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_601] 0 - 0.11
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fddda70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0.4485718575790688 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.36 Core Time (ms) : 2.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_337] 1 True 0.24
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x591725966400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.04738726197557663 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.53 Core Time (ms) : 6.02 TIDL Subgraphs Processing Time (ms) : 5.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24826941 bytes MEM: Free's : 26 free's of 24826941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_551] 0 - 0.14
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df29e120 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_85] 1 True 0.24
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f31470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1824s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008790513144733565 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.66 Core Time (ms) : 0.64 TIDL Subgraphs Processing Time (ms) : 0.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_789] 0 - 0.15
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7ca6210 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_405] 1 True 0.38
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5286f4ba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12748s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.025534029202035905 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 111.78 Core Time (ms) : 108.57 TIDL Subgraphs Processing Time (ms) : 108.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70579597 bytes MEM: Free's : 26 free's of 70579597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_504] 1 True 0.21
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f2e460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17274s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12379301244578145 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.43 Core Time (ms) : 16.31 TIDL Subgraphs Processing Time (ms) : 16.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906653 bytes MEM: Free's : 26 free's of 32906653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_73] 1 True 0.24
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d411b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8683s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05073663075956075 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.09 Core Time (ms) : 4.07 TIDL Subgraphs Processing Time (ms) : 4.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_186] 1 True 0.24
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb01248f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.024656948947006187 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.84 Core Time (ms) : 2.82 TIDL Subgraphs Processing Time (ms) : 2.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_69] 1 True 0.22
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f1b3cd8660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1688s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1691s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.023893860344369307 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.87 Core Time (ms) : 14.84 TIDL Subgraphs Processing Time (ms) : 14.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_488] 1 True 0.22
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7685020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.10484125402723074 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.94 Core Time (ms) : 25.56 TIDL Subgraphs Processing Time (ms) : 25.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32994205 bytes MEM: Free's : 26 free's of 32994205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_470] 1 True 0.37
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x566386175470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.76s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3766s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3768s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.03740144933373824 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 49.31 Core Time (ms) : 47.30 TIDL Subgraphs Processing Time (ms) : 47.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40728413 bytes MEM: Free's : 26 free's of 40728413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_243] 1 True 0.22
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e2f2bc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1820s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.14169951851522491 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.73 Core Time (ms) : 1.60 TIDL Subgraphs Processing Time (ms) : 1.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14749629 bytes MEM: Free's : 26 free's of 14749629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_530] 1 True 0.41
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b04db170 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1551s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1553s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1082618118432861 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 58.50 Core Time (ms) : 53.57 TIDL Subgraphs Processing Time (ms) : 53.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 67800765 bytes MEM: Free's : 26 free's of 67800765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_44] 1 True 0.19
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f7ca4e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1434s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1436s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.30571158024609485 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.75 Core Time (ms) : 3.73 TIDL Subgraphs Processing Time (ms) : 3.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_429] 1 True 0.59
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60c88160 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1558s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1560s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0010469237841244864 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 92.77 Core Time (ms) : 89.31 TIDL Subgraphs Processing Time (ms) : 89.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395237 bytes MEM: Free's : 26 free's of 72395237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_262] 1 True 0.23
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a4334a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.131s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11614203310994152 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.49 Core Time (ms) : 5.34 TIDL Subgraphs Processing Time (ms) : 5.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14730685 bytes MEM: Free's : 26 free's of 14730685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_895] 0 - 0.16
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f305839f6b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.07 Core Time (ms) : 6.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_123] 1 True 0.24
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187f32220 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1655s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0011681859988654014 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.20 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12367805 bytes MEM: Free's : 26 free's of 12367805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_570] 0 - 0.14
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f7000127f40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_370] 1 True 0.42
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59172558b480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.011910674503804789 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 91.15 Core Time (ms) : 84.69 TIDL Subgraphs Processing Time (ms) : 84.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52377789 bytes MEM: Free's : 26 free's of 52377789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_857] 0 - 0.21
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f4f9d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_412] 1 True 0.46
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x595a46337b10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3325s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3327s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.310612247263078 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 62.12 Core Time (ms) : 50.50 TIDL Subgraphs Processing Time (ms) : 50.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 72395749 bytes MEM: Free's : 26 free's of 72395749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_24] 1 True 0.22
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x59ef7d413240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1186832453446381 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.16 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332537 bytes MEM: Free's : 26 free's of 12332537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_820] 0 - 0.17
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb003cc80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_690] 0 - 0.25
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69eaa3480 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.95 Core Time (ms) : 11.95 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_219] 1 True 0.21
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2f9ec390 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0742681287387387 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.82 Core Time (ms) : 0.76 TIDL Subgraphs Processing Time (ms) : 0.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13371197 bytes MEM: Free's : 26 free's of 13371197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_614] 0 - 0.09
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df6801f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_572] 0 - 0.08
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fff15c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_21] 1 True 0.24
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57f7e7a6fe50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07972063294498753 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.13 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332537 bytes MEM: Free's : 26 free's of 12332537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_107] 1 True 0.16
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3d89b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1582s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1584s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.1324561975662177 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.14 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12334165 bytes MEM: Free's : 26 free's of 12334165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_345] 1 True 0.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058489680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2129s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.08682264258896155 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.72 Core Time (ms) : 6.24 TIDL Subgraphs Processing Time (ms) : 6.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825277 bytes MEM: Free's : 26 free's of 24825277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_919] 0 - 0.16
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a427fff0a00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_839] 0 - 0.17
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004e56c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 28.07 Core Time (ms) : 28.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_371] 1 True 0.24
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df662560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1546s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.038016796981993825 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.67 Core Time (ms) : 20.92 TIDL Subgraphs Processing Time (ms) : 20.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181949 bytes MEM: Free's : 26 free's of 52181949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_404] 1 True 0.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5286f4bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9278s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.14453846925068906 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.41 Core Time (ms) : 45.07 TIDL Subgraphs Processing Time (ms) : 44.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 70877965 bytes MEM: Free's : 26 free's of 70877965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_805] 0 - 0.09
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c187e4c340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_850] 0 - 0.14
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f50b60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_840] 0 - 0.15
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb01411d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_16] 1 True 0.23
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5edb2fad9d50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.30653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.30698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.30733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.30754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.30784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.30810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.30833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.30852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.30881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.30905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.30923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.30947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.30970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.30993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.31023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.31043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.31062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.31085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.31104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.31129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.31156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.31182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.31200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.31224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.31300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.31322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.31346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.31365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.31384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.31406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.31434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.31457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.31483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.31501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.31521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.31544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.31570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.31589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.31615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.31638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.31662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.31665s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.31667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.025570280379101144 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.75 Core Time (ms) : 1.74 TIDL Subgraphs Processing Time (ms) : 1.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12332665 bytes MEM: Free's : 26 free's of 12332665 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_336] 1 True 0.24
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f1f9860 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2024s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2027s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008637546629106591 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.24 Core Time (ms) : 10.74 TIDL Subgraphs Processing Time (ms) : 10.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24826941 bytes MEM: Free's : 26 free's of 24826941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_74] 1 True 0.27
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f69b08c2000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.19936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.19954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.19972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.19985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.20299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.20312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.20324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.20336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.20352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.20361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.20371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.20388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.20398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20485s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20487s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005396784370905601 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.76 Core Time (ms) : 5.74 TIDL Subgraphs Processing Time (ms) : 5.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_224] 1 True 0.20
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x60e69e9b9da0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1454s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.15462393330754487 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.75 Core Time (ms) : 15.68 TIDL Subgraphs Processing Time (ms) : 15.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13370813 bytes MEM: Free's : 26 free's of 13370813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_501] 1 True 0.26
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5a42800dc110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.11339133115939412 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.92 Core Time (ms) : 21.36 TIDL Subgraphs Processing Time (ms) : 21.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 32906653 bytes MEM: Free's : 26 free's of 32906653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_58] 1 True 0.29
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f70004c8e70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1637s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1638s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.013370425617500717 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.63 Core Time (ms) : 0.61 TIDL Subgraphs Processing Time (ms) : 0.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_633] 0 - 0.14
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x57c188116b10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_616] 0 - 0.10
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5f3058496820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_34] 1 True 0.14
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56638617a930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.15090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.15113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.15146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.15168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.15194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.15221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.15241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.15261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.15288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.15316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15955s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.008233840270237361 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.79 Core Time (ms) : 1.76 TIDL Subgraphs Processing Time (ms) : 1.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12329213 bytes MEM: Free's : 26 free's of 12329213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_83] 1 True 0.20
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5863f6f34e70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.131s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.07556120021135189 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.57 Core Time (ms) : 3.54 TIDL Subgraphs Processing Time (ms) : 3.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328757 bytes MEM: Free's : 26 free's of 12328757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_695] 0 - 0.12
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x6287df663b10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.33 Core Time (ms) : 3.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_340] 1 True 0.17
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5917259688c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12488s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12490s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0891901140803792 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.48 Core Time (ms) : 19.97 TIDL Subgraphs Processing Time (ms) : 19.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24825661 bytes MEM: Free's : 26 free's of 24825661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_171] 1 True 0.14
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x615cb0128b70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1603s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.060695025596729374 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.19 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12403133 bytes MEM: Free's : 26 free's of 12403133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_385] 1 True 0.20
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x634f4e3dd210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1591s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0855725876128829 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.21 Core Time (ms) : 31.40 TIDL Subgraphs Processing Time (ms) : 31.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52181437 bytes MEM: Free's : 26 free's of 52181437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_86] 1 True 0.15
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x58f02a524640 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.3350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.002750735138344228 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.22 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12328885 bytes MEM: Free's : 26 free's of 12328885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_560] 0 - 0.07
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62d5286e9bf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_326] 1 True 0.15
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x56f3f794a280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8389s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.15107055063270933 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.62 Core Time (ms) : 9.33 TIDL Subgraphs Processing Time (ms) : 9.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24978621 bytes MEM: Free's : 26 free's of 24978621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_904] 0 - 0.10
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x5b5c7f111520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_912] 0 - 0.08
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x62ee60ba00b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00
Passed test_tidl_unit.py::test_tidl_unit_operator[ScatterND_241] 1 True 0.08
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
libtidl_onnxrt_EP loaded 0x653ebbb33620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1426s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.4448164840061445 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.35 Core Time (ms) : 1.24 TIDL Subgraphs Processing Time (ms) : 1.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14788029 bytes MEM: Free's : 26 free's of 14788029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!